CSE 140, Fall 2002, Tentative Outlines, CK Cheng, September 2002

Part 0. Introduction (1)

Overall view of digital logic designs

Part 1. Combinational logic

I. specification

1). language, 2) Boolean algebra 3). truth table, 4). switching expression, 5). incompletely specified functions, 6). definitions.

key words: laws of Boolean algebra, minterms, maxterms, sum of products, and product of sums.

II. implementation (2,3,4)

1). Karnaugh maps

i. 2-variable K-map, ii. 3-variable K-map, iii. 4-variable K-map

key words: minterms, product terms, adjacency, neighborhood.

iv. logic minimization (sum of products), v. logic minimization (product of sums).

key words: primes and essential primes

2). Quine-McCluskey method

key words: prime implicant chart and comparison with K-map approach, revisit of the function specification.

III. other types of gates (5)

1). exclusive OR gates,

2). NAND, NOR gates,

3). block diagram transformation,

4). universal set of gates.

key words: extension of AND, OR, NOT gates and Boolean algebra.

Part 2. Sequential Networks (6,7)

I. flip-flop components

1). SR f-f (logic diagram, state table, state diagram, characteristic equation),

2). D f-f,

3). JK f-f,

4). T f-f.

key words: concept of states, relations between f-fs.

5). timing, set up time and hold time.

II. specification (8)

1). language, 2). state diagram, 3). state table, 4). net list, 5). derivation from net list to state diagram, 6). derivation from language description to state diagram.

key words: concept of states in net list

III. implementation (9,10)

1). Mealy machine, 2). Moore machine, 3). excitation table.

key words: derivation of f-f inputs.

IV. state minimization (11)

equivalent states, minimization process.

key words: relation of initial states and input/output sequences.

Part 3. Standard Modules

I. standard combinational modules (12,13)

1). decoder (description, logic diagram, applications),

2). encoder,

3). multiplexer,

4). ROM,

5). PLA,

6). demultiplexer,

7). barrel shifter.

II. adders (14,15)

1). data representation,

2). binary adder,

3). half adder,

4). full adder,

5). serial adder,

6). carry lookahead adder.

III. standard sequential components (16,17)

1). registers,

2). shift registers,

3). counters.

key words: cascade, modulo-n, twisted tail, programmable counters

Part 4. System Designs (18,19)

1). data subsystem, control subsystem,

2). hardware language,

3). design examples,

4). miscellaneous.

key words: data path, control signals, one-hot machine, conditions