| CSE 140 Fall 2001: (tue & thu 935am-10:55am HSS 1330) |
| Text book: Contemporary Logic Design by Randy H. Katz |
| Instructor: |
Isaac Chu,
ichu@cs.ucsd.edu
Office hour @apm2331 T/Th 11am-12pm & by appointment
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TA office hours will start on 2nd week.
Course work:
Objective of this course is to introduce digital components and digital systems
designs. Following are the subjects to be discussed this quarter:
- Switch Networks, Boolean Algebra, and K-maps.
- 2-Level Logic, Multi-level Logic
- Hazards, Multiplexer, and De-multiplexer
- CMOS - what's inside these logic gates
- Programmable Arrays of Logic Gates (ROM, PLA, PAL)
- Sequential Logic Design: Latches, Flip-flops, Registers.
- Counters
- State Machines Designs (Mealy and Moore)
- State Optimization
- Datapath and Control
- Physical layout issues in digital designs.
- Arithmetic Circuits will be covered in
140L
hw problems :
Please attend monday's discussion sections mondays 650pm-740pm @CSB002 (starting 2nd week) where TA will work out some
solutions and answer questions.
*Due 4th week tuesday:
- ch1(8,9,10)
- ch2(10,13,19ab)
- ch3(8de,16ab)
- ch4(9,15a,16ab)
- ROM, PLA & PAL for: F1=A+B'C, F2=AC'+AB, F3=B'C+AC, F4=AC'+B'C
- CMOS: use minimum # of gates for (1) F= A(B+C)' (2) F=AB+C (3) F=(A(BC+D))'
*Due 8th week tuesday:
- ch6(11abc,13ab,16,17,18,19)
- ch7(10ab,11abc)
- ch8(22-draw state diagram)
*Due 10th week thursday:
*Note, hw questions are subject to change according to the lecture progress.
Any changes would be announced in class & updated on the web.
Grading:
- 2 midterms (25% each - 10/18, 11/15)
- hw - 10%
- final exam - 40%
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