C.K. Cheng, J. Lillis, S. Lin, N. Chang, Interconnect Analysis and Synthesis, John-Wiley, 2000, Japanese version edited by H. Onodera, 2003, ISBN4-563-06718-0 C3005, Chinese version edited by W. Yu, 2008, ISBN978-7-302-15732-8.
Z. Feng, B. Yao, and C.K. Cheng, Floorplan Representation in VLSI, Handbook of DATA Structures and Applications, by D.P. Mehta and S. Sahni, Chapman & Hall/CRC, pp. 53-1: 53-29, 2004. A survey of floorplanning representations.
1. C.K. Cheng and E.S. Kuh, "Module Placement Based on Resistive Network Optimi zation," IEEE Trans. on Computer-Aided Design, vol. CAD-3, pp. 218-225, July 1984. A first analytic placement that utilizes the sparsity of VLSI circuitry to embrace the growing complexity due to the scaling of Moore's law.
4. C.K. Cheng and T.C. Hu, "Ancestor Tree for Multi-Terminal Cut Functions," Tech. Report no. CS89-148, Univ. of California, San Diego, July 1989, Annals of Operations Research, vol. 33, pp. 199-213, 1991. A generalization of Gomory and Hu's cut tree for arbitrary symmetric cuts. The work was presented at an event in honor of Gomory for his research contributions.
14. R. Carden and C.K. Cheng, "A Global Router with a Theoretical Bound on the Optimal Solution," IEEE Trans. on CAD, pp. 208-216, Feb. 1996. A first global routing method using multicommodity network flow approaches with theoretical bounds.
23. L.T. Liu, M.T. Kuo, C.K. Cheng, and T.C. Hu, "A Replication Cut for Two-Way Partitioning," IEEE Trans. on CAD, pp. 623-630, May 1995. A first optimal replication cuts using primal dual approaches.
37. S. Chen and C.K. Cheng, " Tutorial on VLSI Partitioning, " VLSI Design, pp. 175-218, vol. 11, no. 3, 2000. A survey of partitioning methods.
38. P.N. Guo, T. Takahashi, C.K. Cheng, and T. Yoshimura, " Floorplanning using a Tree Representation, " IEEE Trans. on CAD, pp. 281-289, Feb. 2001. An O-tree representation that drastically reduce the complexity of the floorlanning structure.
41. B. Yao, H. Chen, C.K. Cheng, and R. Graham, "Floorplan Representations: Complexity and Connections," ACM Trans. on Design Automation of Electronic Systems, vol. 8, pp. 55-80, Jan. 2003. An overview/unification of floorplanning representations.
46. H. Chen, C.K. Cheng, A.B. Kahng, I. Mandoiu, Q. Wang and B. Yao, "The Y-Architecture for On-Chip Interconnect: Evaluations and Methodologies," IEEE Trans. on Computer Aided Design, pp. 588-599, April 2005. A methodology/framework for packaging layout that mimics the honeycomb patterns.
49. S. Zhou, B. Yao, H. Chen, Y. Zhu, M. Hutton, T. Collins, S. Srinivasan, N. Chou, P. Suaris, and C.K. Cheng, "Efficient Timing Analysis with Known False Paths Using Biclique Covering," IEEE Trans. on Computer Aided Design, pp. 959-969, May 2007. A systematic study of the false paths for static timing analysis.
50. H. Zhu, C.K. Cheng, and R. Graham, "On the Construction of Zero-Deficiency Parallel Prefix Adder with Minimum Depth," ACM Trans. on Design Automation of Electronic Systems, pp. 387-409, 2006. An optimal prefix adder architecture with zero-deficiency.
54. Y. Zhu, A. Shayan, W. Zhang, T.L. Chen, T.P. Jung, J.R. Duann, S. Makeig, and C.K. Cheng, "Analyzing High-Density Human Heart Signals using ICA," IEEE Trans. on Biomedical Engineering, pp. 2528-2537, 2008. A sensor array to detect the components and polarities of ECG waves.<\p>
61. Y. Zhang, X. Hu, A. Deutsch, E.E. Engin, J. Buckwalter, C.K. Cheng "Prediction and Comparison of High-Performance On-Chip Global Interconnection," IEEE Trans. on Very Large Scale Integrated Systems, pp. 1154-1166, July 2011.
71. X. Hu, P. Du, S.H. Weng, and C.K. Cheng, "Worst-Case Noise PredictionWith Non-zero Current Transition Times for Power Grid Planning," IEEE Trans. on Very Large Scale Integration Systems, pp. 607-620, March 2014. A theoretical study of rogue wave phenomenon in power distribution networks.
74. X. Zhang, Y. Liu, and C.K. Cheng, "Ratio of the Worst-Case Noise and the Impedance of Power Distribution Network," IEEE Trans. on Components, Packaging and Manufacturing Technology, pp. 1325-1334, Aug. 2014.
76. J. Lu, P. Chen, C.C. Chang, L. Sha, D. Huang, C.C. Teng, and C.K. Cheng, "ePlace: Electrostatics based Placement using Fast Fourier Transform and Nesterov's Method," ACM Trans. on Design Automation of Electronic Systems, 17:1-34, Feb. 2015. An analytical placement using the analogy of eletronic repulsive force.
78. X. Zhang, Y.T. Wang, Y. Wang, T.P. Jung, M.X. Huang C.K. Cheng and A. Mandell, "Ultra-Slow Frequency Bands Reflecting Potential Coherence Between Neocortical Brain Regions," Neuroscience, 289, pp. 71-84, January 2015. One of rare findings on the biomarker of schizophrenia using less than 1Hz MEG waves.
82. H. Zhuang, X. Wang, Q. Chen, P. Chen, and C.K. Cheng, "From Circuit Theory, Simulation to SPICE_Diego: A Matrix Exponential Approach for Time-Domain Analysis of Large-Scale Circuits," IEEE Circuits and Systems Magazine, pp. 16-34, issue 2, 2016. A summary of our work on matrix exponential approach for transient analysis.
88. J. Ramírez, D. Rodriquez, F. Qiao, J. Warchall, J. Rye, E. Aklile, A.S.C. Chiang, B.C. Marin, P.P. Mercier, C.K. Cheng, K.A. Hutcheson, E.H. Shinn, and D.J. Lipomi, "Metallic Nanoislands on Graphene for Monitoring Swallowing Activity in Head and Neck Cancer Patients." ACS nano 12, no. 6: 5913-5922, 2018.
89. P.W. Chen, C.K. Cheng, and X. Wang, "Stability and Convergency Exploration of Matrix Exponential Integration on Power Delivery Network Transient Simulation," IEEE Trans. on Computer Aided Design, pp. 2735-2748, 2019.
90. C.K. Cheng, S. Gao, C. Holtz, I. Kang, Daeyeal Lee, Bill Lin, and Dongwon Park, P.W. Chen, C.K. Cheng, and X. Wang, "Grid-based Framework for Routability Analysis and Diagnosis with Conditional Design Rules," IEEE Trans. on Computer Aided Design, 2020.
93. D. Lee, D. Park, B. Lin, C.K. Cheng, "SP&R: SMT-based Simultaneous Place-&-Route for Standard Cell Synthesis of Advanced Nodes," IEEE Trans. on Computer Aided Design, pp. 2142-2155, 2020.
94. P. Chen, C.K. Cheng, and X. Wang, "Arnoldi Algorithms with Structured Orthogonalization," SIAM Journal on Numerical Analysis, pp. 370-400, 2021. Resolving a stability issue of matrix exponential method.
97. C.K. Cheng, C. Ho, D. Lee, B. Lin, and D. Park "Complementary-FET (CFET) Standard Cell Synthesis Framework for Design and System Technology Co-Optimization using SMT," IEEE Trans. on VLSI, pp. 1178-1191, 2021.
99. D. Lee, C.T. Ho, I. Kang, S. Gao, B. Lin, and C.K. Cheng, "Many-Tier Vertical Gate-All-Around Nanowire FET Standard Cell Synthesis for Advanced Technology Nodes," IEEE Journal of Exploratory Solid-State Computational Devices and Circuits, 2021, Open Access.
102. B. Polat, L. Becerra, P.Y. Hsu, V. Kaipu, P. Mercier, C.K. Cheng, D. Lipomi, "Epidermal Graphene Sensors and Machine Learning for Estimating Swallowed Volume," ACS Applied Nano Materials, ACS Editors' choice 2021 which is a significant honor/award, given only to 365 papers per year across the entire portfolio of 50+ journals published by ACS.
108. C.K. Cheng, C. Ho, D. Lee, and B. Lin, "Monolithic 3D Semiconductor Footprint Scaling Exploration based on VFET Standard Cell Layout Methodology, Design Flow, and EDA Platform,", IEEE Open Access 2022. Explore pin density bottleneck for VFET technologies.