1. C.K. Cheng and A. Kahng, Rapid Prototyping Systems, Wiley Encyclopedia of Electrical and Electronics Engineering, by J. G. Webster, vol. 18, pp. 234-242, 1999.

2. C.K. Cheng, J. Lillis, S. Lin, N. Chang, Interconnect Analysis and Synthesis, John-Wiley, 2000, Japanese version edited by H. Onodera, 2003, ISBN4-563-06718-0 C3005, Chinese version edited by W. Yu, 2008, ISBN978-7-302-15732-8.

3. C.K. Cheng, Z. Qin, and S. Tan, Symbolic Analysis and Reduction of VLSI Circuits, Springer, 2004.

4. Z. Feng, B. Yao, and C.K. Cheng, Floorplan Representation in VLSI, Handbook of DATA Structures and Applications, by D.P. Mehta and S. Sahni, Chapman & Hall/CRC, pp. 53-1: 53-29, 2004.

5. C.K. Cheng, A.B. Kahng, and P.H.W. Leong, "Reconfigurable Computing," Wiley Encyclopedia of Electrical and Electronics Engineering, by J. G. Webster, the second edition.

6. C.K. Cheng, X. Hu, A. Shayan, "Chapter 5: Power Integrity Degradation and Modeling, and Chapter 6: Lumped Distributed and 3D Modeling for Power Integrity," in the book entitled Power Integrity for Nanscale Integrated Systems, edited by M. Hashimoto and R. Nair, published by McGraw Hill, 2013.

7. D. Boland, C.K. Cheng, A.B. Kahng, and P.H.W. Leong, "Reconfigurable Computing," Wiley Encyclopedia of Electrical and Electronics Engineering, by J. G. Webster, pp. 1-17, third edition, online: 2017.

8. C.K. Cheng, Forward in the book entitled Advanced Model Order Reduction Techniques in VLSI Design by S.X.D. Tan and L. He, Cambridge, 2007.

9. C.K. Cheng, Forward in the book entitled Advanced Field-Solver Techniques for RC Extraction of Integrated Circuits by W. Yu and X. Wang, Springer, 2014.

10. C.K. Cheng, C. Ho, and C. Holtz, "SPICE," to appear in Encyclopedia of RF and Microwave Engineering, Edited by C. Rodenbeck.

1. C.K. Cheng and E.S. Kuh, "Module Placement Based on Resistive Network Optimi zation," IEEE Trans. on Computer-Aided Design, vol. CAD-3, pp. 218-225, July 1984.

2. C.K. Cheng, "Linear Placement Algorithms and Applications to VLSI Design," Net works, vol. 17, pp. 439-464, Winter 1987.

3. C.K. Cheng and T.C. Hu, "Maximum Concurrent Flow and Minimum Ratio Cut," Algorithmica, vol. 8, pp. 233-249, 1992.

4. C.K. Cheng and T.C. Hu, "Ancestor Tree for Multi-Terminal Cut Functions," Tech. Report no. CS89-148, Univ. of California, San Diego, July 1989, Annals of Opera tions Research, vol. 33, pp. 199-213, 1991.

5. C.K. Cheng, D.N. Deutsch, C. Shohara, M. Taparauskas and M. Bubien, "Geometric Compaction on Channel Routing," IEEE Trans. on Computer-Aided Design, vol. 11, pp. 115-127, Jan. 1992.

6. C.K. Cheng, S.Z. Yao and T.C. Hu, "The Orientation of Modules Based on Graph Decompositions," IEEE Trans. on Computers, vol. 40, pp. 774-780, June 1991.

7. Y.C. Wei and C.K. Cheng, "Ratio Cut Partitioning for Hierarchical Designs," IEEE Trans. on Computer-Aided Design, vol. 10, pp. 911-921, July 1991.

8. C.K. Cheng and Y.C. Wei, "An Improved Two-Way Partitioning Algorithm with Stable Performance," IEEE Trans. on Computer-Aided Design, pp. 1502-1511, December 1991.

9. Y.C. Wei, C.K. Cheng and Z. Wurman, "Multiple Level Partitioning: An Applica tion to The Very Large Scale Hardware Simulators," IEEE Journal of Solid State Circuits, vol. 26, pp. 706-716, May 1991.

10. C.K. Cheng, X. Deng, Y.Z. Liao and S.Z. Yao, "Symbolic Layout Compaction under Conditional Design Rules," IEEE Trans. on Computer-Aided Design, vol. 11, pp. 475-486, April 1992.

11. C.K. Cheng "The Optimal Partitioning of Networks," Networks, vol. 22, pp. 297- 315, 1992.

12. T. Hamada, C.K. Cheng and P. Chau, "An Efficient Multi-Level Placement Tech nique Using Hierarchical Partitioning," IEEE Trans. on Circuits and Systems, vol. 39, pp. 432-439, June 1992.

13. C. Yeh, C.K. Cheng, and T.T. Lin, "A General Purpose Multiple Way Partitioning Algorithm," IEEE Trans. on CAD, vol. 13, pp. 1480-1488, Dec. 1994.

14. R. Carden and C.K. Cheng, "A Global Router with a Theoretical Bound on the Optimal Solution," IEEE Trans. on CAD, pp. 208-216, Feb. 1996.

15. C. Yeh, L.T. Liu, C.K. Cheng, T.C. Hu, S. Ahmed, and M. Liddel "Block-Oriented Programmable Design with Switching Network Interconnect," IEEE Trans. on VLSI Systems, pp. 45-53, March 1994.

16. S.Z. Yao, N.C. Chou, C.K. Cheng, and T.C. Hu "A Multi-Probe Approach for MCM Substrate Testing," IEEE Trans. on Computer-Aided Design, vol. 13, pp. 110-121, Jan. 1994.

17. C. Yeh, C. K. Cheng and T. T. Lin, "Optimization by Iterative Improvement: An Experimental Evaluation on Two-Way Partitioning," IEEE Trans. on CAD, pp. 145-153, Feb. 1995.

18. C. Yeh, C. K. Cheng and T. T. Lin, "Circuit Clustering Using A Stochastic Flow Injection Method," IEEE Trans. on CAD, pp. 154-162, Feb. 1995.

19. N. C. Chou and C. K. Cheng, "On General Zero-Skew Clock Net Construction," IEEE Trans. on VLSI Systems, pp. 141-146, March 1995.

20. N. C. Chou, C. K. Cheng, and T. Russell, "Dynamic Probe Scheduling Optimization for MCM Substrate Test," IEEE Trans. on Components, Hybrids, and Manufactur ing Tech., pp. 182-189, May 1994.

21. S. Z. Yao, C. K. Cheng, D. Dutt, S. Nahar, and C. Y. Lo, "A Cell-Based Hierarchi cal Pitchmatching Compaction Using Minimal LP," IEEE Trans. on CAD, pp. 523- 526, April 1995.

22. D. Zaleta, J. Fan, B.C. Kress, S.H. Lee, and C. K. Cheng, "Optimum Placement for Optoelectronic MultiChip Modules and the Synthesis of Diffractive Optics for Mul tichip Module Interconnects", Applied Optics, pp. 1444-1456, March 1994.

23. L.T. Liu, M.T. Kuo, C.K. Cheng, and T.C. Hu, "A Replication Cut for Two-Way Partitioning," IEEE Trans. on CAD, pp. 623-630, May 1995.

24. J. Fan, D. Zaleta, C.K. Cheng, and S.H. Lee, "Physical Models and Algorithms for Optoelectronic MCM Layout," IEEE Trans. on VLSI Systems, pp. 124-135, March 1995.

25. N.C. Chou, L.T. Liu, C.K. Cheng, W.J. Dai, and R. Lindelof, "Local Ratio Cut and Set Covering Partitioning for Huge Logic Emulation Systems," IEEE Trans. on CAD, pp. 1085-1092, Sept. 1995.

26. R. Carden and C.K. Cheng, "Early Feasibility and Cost Assessment for MCM Tech niques," Special Issue on High Performance CAD for Packaging and MCMs, Int. Journal of High Speed Electronics and Systems, vol. 6, no. 3, pp. 441-458, 1995.

27. R.J. Carragher, C.K. Cheng, X.M. Xiong, M. Fujita, and R. Paturi, "Solving the Net Matching Problem in High-Performance Chip Design," IEEE Trans. on CAD, pp. 902-911, Aug. 1996.

28. L.T. Liu, M. Shih, J. Lillis, and C.K. Cheng "Data Flow Partitioning for Clock Period and Latency Minimization," IEEE Trans. on CAS, Part I, pp. 210-220, March 1997.

29. J. Lillis, C.K. Cheng, and T.T. Lin, "Optimal Wire Sizing and Buffer Insertion for Low Power and a Generalized Delay Model," IEEE Journal of Solid State Circuits, pp. 437-447, March 1996.

30. T. Hamada, C.K. Cheng, and P. Chau, "A Wire Length Estimation Technique Utilizing Neighborhood Density Equations," IEEE Trans. on CAD, pp. 912-922, Aug. 1996.

31. C.C. Tsai, D.Y. Kao, and C.K. Cheng, "Performance Driven Bus Buffer Insertion," IEEE Trans. on CAD, pp. 429-437, April 1996.

32. X. Hong, T. Xue, J. Huang, C.K. Cheng, and E.S. Kuh, "Tiger: An Efficient Timing-Driven Global Router for Gate Array and Standard Cell Layout Design," ACM/IEEE Design Automation Conf., pp. 177-181, June 1993.

33. J. Li and C.K. Cheng, "Routability Improvement Using Dynamic Interconnect Architecture," IEEE Trans. on VLSI, pp. 498-501, September 1998.

34. J. Xu, P.N. Guo, and C.K. Cheng, " Sequence-Pair Approach for Rectilinear Module Placement, " IEEE Trans. on CAD, pp. 484-493, April 1999.

35. J. Xu, P.N. Guo, and C.K. Cheng, " Empirical Study of Block Placement by Cluster Refinement," VLSI Design, vol. 10, no. 1, pp. 71-86, 1999.

36. J. Lillis and C.K. Cheng, " Timing Optimization for Multisource Nets: Characterization and Optimal Repeater Insertion, " IEEE Trans. on CAD, pp. 322-331, March, 1999.

37. S. Chen and C.K. Cheng, " Tutorial on VLSI Partitioning, " VLSI Design, pp. 175-218, vol. 11, no. 3, 2000.

38. P.N. Guo, T. Takahashi, C.K. Cheng, and T. Yoshimura, " Floorplanning using a Tree Representation, " IEEE Trans. on CAD, pp. 281-289, Feb. 2001.

39. X.D. Yang, C.K. Cheng, W.H. Ku, and R.J. Carragher, " Reduced Order Modeling for RLC Interconnect using Hurwitz Polynomials, " IEEE Journal of Analog Integrated Circuits and Signal Processing, vol. 31, no.3, pp. 193-208, June 2002.

40. C.K. Cheng, A.B. Kahng, B. Liu, and D. Stroobandt, "Toward Better Wireload Models in the Presence of Obstacles," IEEE Trans. on VLSI, pp. 177-189, April 2002.

41. B. Yao, H. Chen, C.K. Cheng, and R. Graham, "Floorplan Representations: Complexity and Connections," ACM Trans. on Design Automation of Electronic Systems, vol. 8, pp. 55-80, Jan. 2003.

42. T. Jing, X. Hong, J. Xu, H. Bao, C.K. Cheng, and J. Gu, "UTACO: A Unified Timing and Congestion Optimization Algorithm for Standard Cell Global Routing," IEEE Trans. on CAD, pp. 358-365, March 2004.

43. X. Wu, X. Hong, Y. Cai, Z. Luo, C.K. Cheng, J. Gu, and W. Dai, "Area Minimization of Power Distribution Network Using Efficient Nonlinear Programming Techniques," IEEE Trans. on CAD, pp. 1086-1094, July 2004.

44. T. Takahashi, P.N. Guo, C.K. Cheng, and T. Yoshimura, "Floorplanning using a Tree Representation: A Summary," IEEE Circuits and Systems Magazine, pp. 26-29, vo. 3, no. 2, 2003.

45. C.W. Chang, M.F. Hsiao, B. Hu, K. Wang, M. Marek-Sadowska, C.K. Cheng, and S.J. Chen, "Fast Postplacement Optimization Using Functional Symmetries," IEEE Trans. on Computer-Aided Design, pp. 102-118, Jan. 2004.

46. H. Chen, C.K. Cheng, A.B. Kahng, I. Mandoiu, Q. Wang and B. Yao, "The Y-Architecture for On-Chip Interconnect: Evaluations and Methodologies," IEEE Trans. on Computer Aided Design, pp. 588-599, April 2005.

47. Y. Ma, X. Hong, S. Dong, S. Chen, C.K. Cheng, and J. Gu, "Buffer Planning as an Integral Part of Floorplanning with Consideration of Routing Congestion," IEEE Trans. on Computer Aided Design, pp. 609-621, April 2005.

48. Z. Zhu, H. Peng, K. Rouz, M. Borah, C.K. Cheng and E.S. Kuh, "Two-Stage Newton-Raphson Method for Transistor Level Simulation," IEEE Trans. on Computer Aided Design, pp. 881-895, May 2007.

49. S. Zhou, B. Yao, H. Chen, Y. Zhu, M. Hutton, T. Collins, S. Srinivasan, N. Chou, P. Suaris, and C.K. Cheng, "Efficient Timing Analysis with Known False Paths Using Biclique Covering," IEEE Trans. on Computer Aided Design, pp. 959-969, May 2007.

50. H. Zhu, C.K. Cheng, and R. Graham, "On the Construction of Zero-Deficiency Parallel Prefix Adder with Minimum Depth," ACM Trans. on Design Automation of Electronic Systems, pp. 387-409, 2006.

51. Z. Li, X. Hong, Q. Zhou, Y. Cai, J. Bian, H.H. Yang, V. Pitchumani, and C.K. Cheng, "Hierarchical 3-D Floorplanning Algorithm for Wirelength Optimization," IEEE Trans. on Circuits and Systems, pp. 2637-2646, Dec. 2006.

52. S. Chen, S.Q. Dong, X.L. Hong, Y.C. Ma, C.K. Cheng, "VLSI Block Placement with Alignment Constraints," IEEE Trans. on Circuits and Systems, II-Express Briefs, 53 (8): pp. 622-626, Aug. 2006.

53. Y. Zhu, T. Weng, C.K. Cheng, "Enhancing Learning Effectiveness in Digital Design Courses by Programmable Logic Boards," IEEE Trans. on Education, pp. 151-156, Feb. 2009.

54. Y. Zhu, A. Shayan, W. Zhang, T.L. Chen, T.P. Jung, J.R. Duann, S. Makeig, and C.K. Cheng, "Analyzing High-Density Human Heart Signals using ICA," IEEE Trans. on Biomedical Engineering, pp. 2528-2537, 2008.

55. Y. Zhu, Y. Hu, M.B. Taylor and C.K. Cheng, "Energy and Switch Area Optimizations for FPGA Global Routing Architectures," ACM Trans. on Design Automation of Electronic Systems, pp. 13-25, Jan. 2009.

56. M. Hashimoto, J. Siriporn, A. Tsuchiya, H. Zhu, and C.K. Cheng, "Analytical Eye-diagram Model for On-chip Distortionless Transmission Lines and Its Application to Design Space Exploration," Institute of Electronics, Information and Communication Engineers Trans., pp. 3474-3480, Dec. 2008

57. W. Yu, R. Shi, and C.K. Cheng, "Accurate Eye Diagram Prediction Based on Step Response and Its Application to Low-Power Equalizer Design Date of Evaluation," IEICE Trans. Electron, pp. 444-452, April 2009.

58. S. Zeng, W. Yu, J. Shi, X. Hong, and C.K. Cheng, "Efficient Partial Reluctance Extraction for Large-Sacel Regular Power Grid Structures," IEICE Trans. on Fundamentals, Vol. E92-A, No.6 pp. 1479-1484, Jun. 2009

59. W. Zhang, W. Yu, L. Zhang, R. Shi, H. Peng, Z. Zhu, L. Chua-Eoan, R. Murgai, T. Shibuya, N. Ito, and C.K. Cheng, "Efficient Power Network Analysis Considering Multi-Domain Clock Gating," IEEE Trans on CAD, pp. 1348-1358, Sept. 2009.

60. L. Zhang, Y. Zhang, H. Cheng, B. Yao, K. Hamilton, and C.K. Cheng, "On-Chip Interconnect Analysis of Performance and Energy Metrics under Different Design Goals," IEEE Trans. on Very Large Scale Integration Systems, pp. 520-524, March 2011.

61. Y. Zhang, X. Hu, A. Deutsch, E.E. Engin, J. Buckwalter, C.K. Cheng "Prediction and Comparison of High-Performance On-Chip Global Interconnection," IEEE Trans. on Very Large Scale Integrated Systems, pp. 1154-1166, July 2011.

62. L. Zhang, W. Yu, Y. Zhang, R. Wang, A. Deutsch, G.A. Katopis, D.M. Dreps, J. Buckwalter, E.S. Kuh, and C.K. Cheng, "Analysis and Optimization of Low Power Passive Equalizers for CPU-Memory Links," IEEE Trans. on Components, Packaging, and Manufacturing Technology, pp. 1406-1420, September 2011.

63. R. Wang, E. Young, and C.K. Cheng, "Complexity of 3-D Floorplan by Analysis of Graph Cuboidal Dual Hardness," ACM Trans. on Design Automation of Electronic Systems, vol. 15, no. 4, Sept. 2010.

64. S. Zeng, W. Yu, X. Hong, and C.K. Cheng, "Efficient Power Network Analysis with Modeling of Inductive Effects," IEICE Trans. on Fundamentals, Vol. E93-A, No.6, pp. 1196-1203, Jun. 2010

65. R. Wang, Y. Zhang, N.C. Chou, E.F.Y. Young, C.K. Cheng and R. Graham, "Bus Matrix Synthesis based on Steiner Graphs for Power Efficient System-on-Chip Communications," IEEE Trans. on CAD, pp. 167-179, Feb. 2011.

66. C.K. Cheng, P. Du, X. Hu, A.B. Kahng, G.K.H. Pang, Y. Wang and N. Wong, "A Realistic Early-Stage Power Grid Verification Algorithm Based on Hierarchical Constraints," IEEE Trans. on Computer-Aided Design, pp.109-120, Jan. 2012.

67. X. Hu, P. Du, J. Buckwalter, and C.K. Cheng, "Modeling and Analysis of Power Distribution Networks in 3D ICs," IEEE Trans. on VLSI, pp. 354-366, Feb. 2013.

68. Q. Chen, S.H. Weng, and C.K. Cheng, "A Practical Regularization Technique for Modified Nodal Analysis in Large-Scale Time-Domain Circuit Simulation," IEEE Trans. on Computer-Aided Design, pp. 1031-1040, July 2012.

69. S.H. Weng, Q. Chen and C.K. Cheng, "Time-Domain Analysis of Large-Scale Circuits by Matrix Exponential Method with Adaptive Control," IEEE Trans. on Computer-Aided Design, pp. 1180-1193, 2012.

70. H.H. Chuang, YL Cheng, C.K. Cheng, and T.L. Wu, "A Novel Differential-Mode Equalizer with Broadband Common-Mode Filtering for Gbps Differential-Signal Transmission," IEEE Trans. on Components, Packaging and Manufacturing Technology, pp. 1578-1587, Sept., 2013.

71. X. Hu, P. Du, S.H. Weng, and C.K. Cheng, "Worst-Case Noise PredictionWith Non-zero Current Transition Times for Power Grid Planning," IEEE Trans. on Very Large Scale Integration Systems, , pp. 607-620, March 2014.

72. X. Huang, L. Huang, T.P. Jung, C.K. Cheng and A. Mandell, "Intrinsic Mode Functions Locate Implicit Turbulent Attractors in Time in Frontal Lobe MEG Recordings," Neuroscience, pp. 91-101, 2014.

73. S.H. Weng, Y. Zhang, J.F. Buckwalter, and C.K. Cheng, "Energy Efficiency Optimization Through Codesign of the Transmitter and Receiver in High-Speed On-Chip Interconnects," IEEE Trans. on Very Large Scale Integration Systems, pp. 938-942, April 2014.

74. X. Zhang, Y. Liu, and C.K. Cheng, "Ratio of the Worst-Case Noise and the Impedance of Power Distribution Network," IEEE Trans. on Components, Packaging and Manufacturing Technology, pp. 1325-1334, Aug. 2014.

75. Y.T. Wang, K.C. Huang, C.S. Wei, T.Y. Huang, L.W. Ko, C.T. Lin, C.K. Cheng, T.P. Jung "Developing an EEG based On-line Closed-loop Lapse Detection and Mitigation System," Frontiers in Neuroscience, pp. 85-95, Oct. 2014.

76. J. Lu, P. Chen, C.C. Chang, L. Sha, D. Huang, C.C. Teng, and C.K. Cheng, "ePlace: Electrostatics based Placement using Fast Fourier Transform and Nesterov's Method," ACM Trans. on Design Automation of Electronic Systems, 17:1-34, Feb. 2015.

77. J. Lu, P. Chen, C.C. Chang, L. Sha, D. Huang, C.C. Teng, and C.K. Cheng, "ePlace-MS: Electrostatics based Placement for Mixed-Size Circuits," IEEE Trans. on Computer-Aided Design, pp. 685-698, May 2015.

78. X. Zhang, Y.T. Wang, Y. Wang, T.P. Jung, M.X. Huang C.K. Cheng and A. Mandell, "Ultra-Slow Frequency Bands Reflecting Potential Coherence Between Neocortical Brain Regions," Neuroscience, 289, pp. 71-84, January 2015.

79. Q. Chen, W. Schoenmaker, S.H. Weng, C.K. Cheng, G.H. Chen, L.J. Jiang and N. Wong, "A Fast Time-Domain EM-TCAD Coupled Simulation Framework via Matrix Exponential with Stiffness Reduction," Int. Journal of Circuit Theory and Applications, pp. 833-850, 2016.

80. Q. Mei, W. Schoemaker, S.H. Weng, H. Zhuang, C.K. Cheng, and Q. Chen, "An Efficient Transient Electro-Thermal Simulation Framework for Power Integrated Circuits," IEEE Trans. on Computer-Aided Design, pp. 832-843, May 2016.

81. C.K. Cheng, in Memoriam of Prof. Ernest Kuh by A. Kuh, IEEE Circuits and Systems Magazine, pp. 8-9, issue 4, 2015.

82. H. Zhuang, X. Wang, Q. Chen, P. Chen, and C.K. Cheng, "From Circuit Theory, Simulation to SPICE_Diego: A Matrix Exponential Approach for Time-Domain Analysis of Large-Scale Circuits," IEEE Circuits and Systems Magazine, pp. 16-34, issue 2, 2016.

83. Y.T. Wang, M. Nakanishi, Y. Wang, C.S. Wei, C.K. Cheng and T.P. Jung "An Online Brain-Computer Interface Based on SSVEPs Measured from Non-Hair-Bearing Areas," IEEE Trans. on Neural Systems & Rehabilitation Engineering, vol. 99, pp. 1-8, 2016.

84. H. Zhuang, W. Yu, S.H. Weng, I. Kang, J.H. Lin, X. Zhang, R. Coutts, and C.K. Cheng, "Simulation Algorithms with Exponential Integration for Time-Domain Analysis of Large-Scale Power Delivery Networks," IEEE Trans. on Computer-Aided Design, pp. 1681-1694, Oct. 2016.

85. M.X. Huang, S. Nichols, A. Robb-Swan, A. Angeles-Quinto, D.L. Harrington, A. Drake, C.W. Huang, T. Song, M. Diwakar, V.B. Risbrough, S. Matthews, R. Clifford, C.K. Cheng, J.W. Huang, A. Sinha, K.A. Yurgil, Z. Ji, I. Lerman, R.R. Lee, and D.G. Baker, "MEG Working Memory N-Back Task Reveals Functional Deficits in Combat-Related Mild Traumatic Brain Injury," Cerebral Cortex, pp. 1953-1968, 2019.

86. C.K. Cheng, A.B. Kahng, I. Kang, L. Wang "RePlAce: Advancing Solution Quality and Routability Validation in Global Placement," IEEE Trans. on Computer-Aided Design, pp. 1717-1730, 2019.

87. I. Kang, F. Qiao, D. Park, D. Kane, E.F.Y. Young, C.K. Cheng and R. Graham, "Three-dimensional Floorplan Representations by Using Corner Links and Partial Order," ACM Trans. on Design Automation of Electronic Systems (TODAES), 24(1), p.13., 2018

88. J. Ramírez, D. Rodriquez, F. Qiao, J. Warchall, J. Rye, E. Aklile, A.S.C. Chiang, B.C. Marin, P.P. Mercier, C.K. Cheng, K.A. Hutcheson, E.H. Shinn, and D.J. Lipomi, "Metallic Nanoislands on Graphene for Monitoring Swallowing Activity in Head and Neck Cancer Patients." ACS nano 12, no. 6: 5913-5922, 2018.

89. P.W. Chen, C.K. Cheng, and X. Wang, "Stability and Convergency Exploration of Matrix Exponential Integration on Power Delivery Network Transient Simulation," IEEE Trans. on Computer Aided Design, pp. 2735-2748, 2019.

90. C.K. Cheng, S. Gao, C. Holtz, I. Kang, Daeyeal Lee, Bill Lin, and Dongwon Park, P.W. Chen, C.K. Cheng, and X. Wang, "Grid-based Framework for Routability Analysis and Diagnosis with Conditional Design Rules," IEEE Trans. on Computer Aided Design, 2020.

91. E. Chang, C.K. Cheng, A. Gupta, P.Y. Hsu, A. Moffitt, A. Ren, I. Tsaur, S. Wang, "Empirical Study on Sufficient Numbers of Minimum Cuts in Strongly Connected Directed Random Graphs," Networks, 2020.

92. M.X. Huang, C.W. Huang, D.L. Harrington, S. Nichols, A. Robb-Swan, A. Angeles-Quinto, L. Le, C. Rimmele, A. Drake, T. Song, J.W. Huang, R. Clifford, Z. Ji, C.K. Cheng, I. Lerman, K.A. Yurgil, R.R. Lee, and D.G. Baker, "Marked Increases in Resting-State MEG Gamma-Band Activity in Combat-Related Mild Traumatic Brain Injury," Cerebral Cortex, pp. 283-295, 2020.

93. D. Lee, D. Park, B. Lin, C.K. Cheng, "SP&R: SMT-based Simultaneous Place-&-Route for Standard Cell Synthesis of Advanced Nodes," IEEE Trans. on Computer Aided Design, pp. 2142-2155, 2020.

94. P. Chen, C.K. Cheng, and X. Wang, "Arnoldi Algorithms with Structured Orthogonalization," SIAM Journal on Numerical Analysis, pp. 370-400, 2021.

95. M.X. Huang, C. Huang, D. Harrington, A. Robb-Swan, A. Angeles-Quinto, S. Nichols, J. Huang, L. Le, C. Rimmele, M. Scott, A. Drake, T. Song, Z. Ji, C.K. Cheng, Q. Shen, E. Foote, I. Lerman, K. Yurgil, H. Hansen, R. Naviaux, R. Dynes, D. Baker, and R. Lee, "Resting-State MEG Source Magnitude Imaging with Deep-Learning Neural Network for Classification of Symptomatic Combat-related Mild Traumatic Brain Injury," Human Brain Mapping, pp. 1987-2004, 2021.

96. D. Lee, B. Lin, and C.K. Cheng, "SMT-based Contention-Free Task Mapping and Scheduling on SMART NoC" IEEE Embedded Systems Letters, 2021.

97. C.K. Cheng, C. Ho, D. Lee, B. Lin, and D. Park "Complementary-FET (CFET) Standard Cell Synthesis Framework for Design and System Technology Co-Optimization using SMT," IEEE Trans. on VLSI, pp. 1178-1191, 2021.

98. H.T. Zhang, M. Fujita, C.K. Cheng, and J.H.R. Jiang, "SAT-Based On-Track Bus Routing," IEEE Trans. on Computer-Aided Design, pp. 735-747, April 2021.

99. D. Lee, C.T. Ho, I. Kang, S. Gao, B. Lin, and C.K. Cheng, "Many-Tier Vertical Gate-All-Around Nanowire FET Standard Cell Synthesis for Advanced Technology Nodes," IEEE Journal of Exploratory Solid-State Computational Devices and Circuits, 2021, Open Access.

100. C.K. Cheng, A.B. Kahng, H. Kim, D. Lee, D. Park, and M. Woo, "PROBE2.0: A Systematic Framework for Routability Assessment from Technology to Design in Advanced Nodes," IEEE Trans. on Computer Aided Design, pp. 1495-1508, 2021.

101. C.K. Cheng, C.T. Ho, D. Lee, and B. Lin, "Multi-row Complementary-FET (CFET) Standard Cell Synthesis Framework using Satisfiability Modulo Theories (SMT)," IEEE Journal of Exploratory Solid-State Computational Devices and Circuits, 2021, Open Access.

102. B. Polat, L. Becerra, P.Y. Hsu, V. Kaipu, P. Mercier, C.K. Cheng, D. Lipomi, "Epidermal Graphene Sensors and Machine Learning for Estimating Swallowed Volume," ACS Applied Nano Materials, pp. 8126-8134, 2021, ACS Editorsâ€™ choice 2021 which is a significant honor/award, given only to 365 papers per year across the entire portfolio of 50+ journals published by ACS.

103. D. Lee, B. Lin, and C.K. Cheng, "SMT-based Contention-Free Task Mapping and Scheduling on 2D/3D SMART NoC with Mixed Dimension-Order Routing," ACM Trans. on Architecture and Code Optimization, pp. 1-21, 2021.

104. D. Lee, B. Lin, and C.K. Cheng, "SMT-based contention-free task mapping and scheduling on SMART NoC. IEEE Embedded Systems Letters, 13(4), pp.158-161, 2021.

105. D.L. Harrington, et al., "Detection of Chronic Blast-related Mild Traumatic Brain Injury with Diï¬€usion Tensor Imaging and Support Vector Machines," Diagnostics, p. 987-17, 2022.

106. CK Cheng, D. Lee, Bill Lin, and C. Ho, "Machine Learning Prediction for Design and System Technology Co-Optimization Sensitivity Analysis," IEEE Trans. on Very Large Scale Integration Systems, pp. 1059-1072, 2022.

107. U. Mallappa, C.K. Cheng, and B. Lin, "Joint Application-Aware Oblivious Routing and Static Virtual Channel Allocation," in IEEE Embedded Systems Letters, 2022.

108. C.K. Cheng, C. Ho, D. Lee, and B. Lin, "Monolithic 3D Semiconductor Footprint Scaling Exploration based on VFET Standard Cell Layout Methodology, Design Flow, and EDA Platform" IEEE Open Access 2022.

109. U. Mallappa, C.K. Cheng, and B. Lin, "JARVA: Joint Application-Aware Oblivious Routing and Static Virtual Channel Allocation," IEEE Design \& Test, vol. 39, issue 6, pp. 16-27, Dec. 2022.

110. C.K. Cheng, C. Holtz, A.B. Kahng, B. Lin, U. Mallappa, "DAGSizer: A Directed Graph Convolutional Network Approach to Discrete Gate Sizing of VLSI Graphs," ACM Trans. on Design Automation of Electronic Systems, 2022.

111. M.X. Huang, A. Angeles-Quinto, A. Robb-Swan, B.G. De-la-Garza, C.W. Huang, C.K. Cheng, J.R. Hesselink, E.D. Biglet, E.A. Wilde, F. Vaida, E.A. Troyer, and J.E. Max, "Assess Pediatric Mild Traumatic Brain Injury and its Recovery using Resting-State MEG Source Magnitude Imaging and Machine Learning," Journal of Neurotrama, 2023.

112. B. Polat, T. Rafeedi, L. Becerra, A.X. Chen, K. Chiang, V. Kaipu, R. Blau, P.P. Mercier, C.K. Cheng, . and D.J. Lipomi, "External Measurement of Swallowed Volume During Exercise Enabled by Stretchable Derivatives of PEDOT: PSS, Graphene, Metallic Nanoparticles, and Machine Learning," Advanced Sensor Research, p.2200060-70, 2023.

1. C.K. Cheng and E.S. Kuh, "Partitioning and Placement Based on Network Optimi zation," IEEE Int. Conf. on Computer-Aided Design, pp. 86-88, 1983.

2. J.T. Li, C.K. Cheng, M. Turner, E.S. Kuh and M. Marek-Sadowska, "Automatic Layout of Gate Arrays," Custom Integrated Circuits Conf., pp. 518-521 May 1984.

3. C.K. Cheng, "Decomposition Algorithms for Linear Placement and Applications to VLSI Design," IEEE Int. Symposium on Circuits and Systems, pp. 1047-1050, June 1985.

4. C.K. Cheng and D.N. Deutsch, "Improved Channel Routing by Via Minimization and Shifting," ACM/IEEE Design Automation Conf., pp. 677-680, June 1988.

5. Y.C. Wei and C.K. Cheng, "Towards Efficient Hierarchical Designs by Ratio Cut Partitioning," IEEE Int. Conf. on Computer-Aided Design, pp. 298-301 Nov. 1989.

6. C.K. Cheng and T.C. Hu, "Ancestor Tree for Arbitrary Multi-Terminal Cut Func tions," Integer Programming/Combinatorial Optimization Conf., Univ. of Waterloo, pp. 115-127, May 1990.

7. C.K. Cheng, T.C. Hu and S.Z. Yao "The Modular Orientation of VLSI Layout," IEEE Symp. on Circuits and Systems, pp. 1600-1603, May 1990.

8. Y.C. Wei and C.K. Cheng, "A Two-Level Two-Way Partitioning Algorithm," IEEE Int. Conf. on Computer-Aided Design, pp. 516-519, Nov. 1990.

9. C.K. Cheng, "The Optimal Circuit Decompositions Using Network Flow Formula tions," IEEE Int. Symp. on Circuits and Systems, pp. 2650-2653, May 1990.

10. R. Carden and C.K. Cheng, "A Global Router Using An Efficient Approximate Multicommodity Multiterminal Flow Algorithm," ACM/IEEE Design Automation Conf., pp. 316-321, July 1991.

11. C. Yeh, C.K. Cheng and T.T. Lin, "A General Purpose Multiple Way Partitioning Algorithm," ACM/IEEE Design Automation Conf., pp. 421-426, July 1991. The paper is nominated for the best paper award (15 out of 454 papers).

12. C.K. Cheng, Y.C. Wei and Z. Wurman "The Mapping of Logic Designs into A Very Large Scale Hardware Simulator," IEEE Int. Symp. on Circuits and Systems, pp. 2036-2039, June 1991.

13. T. Hamada, C.K. Cheng and P. Chau, "An Efficient Multi-Level Placement Tech nique Using Hierarchical Partitioning," IEEE Int. Symp. on Circuits and Systems, pp. 2044-2047, June 1991.

14. C.K. Cheng, X. Deng, Y.Z. Liao and D. Yao, "Discussion on VLSI Layout Com paction with Conditional Constraints," IEEE Int. Symp. on Circuits and Systems, pp. 2132-2135, June 1991.

15. R. Carden, and C.K. Cheng, "Feasibility Estimation and Cost Optimization for Mul tichip Module Technologies," IEEE Int. Conf. on ASIC, P9:1.1-4, Sept. 1991.

16. S.Z. Yao, N.C. Chou, C.K. Cheng and T.C. Hu, "A Multi-Chip Module Substrate Testing Algorithm," IEEE Int. Conf. on ASIC, P9:4.1-4, Sept. 1991.

17. C.W. Yeh, C.K. Cheng, and T.T. Lin, "An Experimental Evaluation of Partitioning Algorithms," IEEE Int. Conf. on ASIC, P14:1.1-4, Sept. 1991.

18. T. Hamada, C.K. Cheng and P. Chau "A Wire Length Estimation Technique Utiliz ing Neighborhood Density Equations," ACM/IEEE Design Automation Conf., pp. 57-61, July 1992.

19. X.L. Hong, J. Huang, C.K. Cheng, and E.S. Kuh, "FARM: An Efficient Feedthrough Pin Assignment Algorithm," ACM/IEEE Design Automation Conf., pp. 530-535, July 1992.

20. C.W. Yeh, L.T. Liu, C.K. Cheng, T.C. Hu, S. Ahmed, and M. Liddel, "Block Oriented Programmable Design with Switching Network Interconnect," Synthesis and Simulation Meeting and International Interchange, Kobe, Japan, pp. 406-414, April 1992.

21. J.W. Chung, R. Carragher, C.K. Cheng, and X.M. Xiong, "Performance Driven Routing Algorithms for Electronic Interconnects," International Workshop on Lay out Synthesis, vol. 2., pp. 155-156, May 1992.

22. N.C. Chou, C.K. Cheng, and T.C. Russell, "High Performance Microelectronic Sub strate Verification Using Probe Testers," IEEE Int. Conf. on ASIC, pp. 230-233, Sept. 1992.

23. S.Z. Yao, N.C. Chou, C.K. Cheng, and T.C. Hu, "An Optimal Probe Testing Algo rithm for The Connectivity Verification of MCM Substrates," IEEE Int. Conf. on Computer-Aided Design, pp. 264-267, Nov. 1992.

24. C.W. Yeh, C.K. Cheng, and T.T. Lin, "A Probabilistic Multicommodity-Flow Solu tion to Circuit Clustering Problems," IEEE Int. Conf. on Computer-Aided Design, pp. 428-431, Nov. 1992.

25. R. Carragher, C.K. Cheng, and X.M. Xiong, "The Net Matching Problem in High Performance Microelectronics Design," ACM/SIGDA Physical Design Workshop, pp. 52-62, April 1993.

26. J. Fan, D. Zaleta, C.K. Cheng, and S.H. Lee, "Physical Layout Algorithms for Com puter Generated Holograms in Optoelectronic MCM Systems Design," IEEE Mul tichip Module Conf., pp. 198-203, March 1993.

27. S.H. Lee, V.H. Ozguz, J. Fan, D. Zaleta, and C.K. Cheng, "Computer Aided Design and Packaging Optoelectronic Systems with Free Space Optical Interconnects," IEEE Custom Integrated Circuits Conf., 29.3.1-4, May 1993.

28. X.M. Xiong, J. Hardin, and C.K. Cheng, "PAS: A Stand Alone Placement Annota tion System for High Speed Designs," IEEE Custom Integrated Circuits Conf., pp. 9.1.1-5, May 1993.

29. T. Hamada, C.K. Cheng, and P. Chau, "PRIME: A Timing-Driven Placement Using A Piecewise Linear Resistive Network Approach," ACM/IEEE Design Automation Conf., pp. 531-536, June 1993.

30. J. Huang, X. Hong, C.K. Cheng, and E.S. Kuh, "An Efficient Timing-Driven Global Routing Algorithm," ACM/IEEE Design Automation Conf., pp. 596-600, June 1993.

31. S.Z. Yao, C.K. Cheng, D. Dutt, S. Nahar, and C.Y. Lo, "Cell-Based Hierarchical Pitchmatching Compaction Using Minimal LP," ACM/IEEE Design Automation Conf., pp. 395-400, June 1993. The paper is nominated for the best paper award (15 out of 453 papers).

32. X. Hong, T. Xue, C.K. Cheng, E.S. Kuh, and J. Huang "Performance-Driven Steiner Tree Algorithms for Global Routing," ACM/IEEE Design Automation Conf., pp. 177-181, June 1993.

33. N.C. Chou and C.K. Cheng, "Performance-Driven Clock Net Routing," Int. Conf. on CAD/Graphics, Beijing, China, pp. 429-434, Aug. 1993.

34. R.J. Carragher, C.K. Cheng, and X.M. Xiong, "The Net Matching Problem in High Performance Microelectronics Design," Int. Conf. on CAD/Graphics, Beijing, China, pp. 546-551, Aug. 1993.

35. J. Fan, S.H. Lee, C.K. Cheng, and T. Hamada, "Free Space Optoelectronic System Placement Based on Quadratic Approximation," Int. Conf. on CAD/Graphics, Beij ing, China, pp. 493-499, Aug. 1993.

36. N.C. Chou and C.K. Cheng, "Wire Length and Delay Minimization in General Clock Net Routing," IEEE Int. Conf. on Computer-Aided Design, pp. 552-555, Nov. 1993.

37. R. Carragher, C.K. Cheng, and M. Fujita, "An Efficient Algorithm for the Net Matching Problem," IEEE Int. Conf. on Computer-Aided Design, pp. 640-644, Nov. 1993.

38. L.T. Liu, M. Shih, N.C. Chou, C.K. Cheng, and W. Ku, "Performance-Driven Parti tioning Using Retiming and Replication," IEEE Int. Conf. on Computer-Aided Design, pp. 296-299, Nov. 1993.

39. X.M. Xiong and C.K. Cheng "Interconnect and Output Driver Modeling of High Speed Designs," IEEE Int. Conf. on ASIC, pp. 507-510, Sept. 1993.

40. R.R. McBride, J. Chung, E.C. Shi, and C.K. Cheng "Pin Redistribution for Mul tichip Module Designs," Int. Symp. on Microelectronics, pp. 605-609, Nov. 1993.

41. N.C. Chou and C.K. Cheng "Optimal Test Size and Efficient Probe Scheduling for Substrate Verification Using Two-Probe Testers," Int. Symp. on Microelectronics, pp. 276-281, Nov. 1993.

42. R. Carragher, N.C. Chou, C.K. Cheng, T. Russell "Distortion Mapping for Cofired Ceramic Substrate Testing," Int. Symp. on Microelectronics, pp. 295-300, Nov. 1993.

43. R. Carragher and C.K. Cheng "Minimizing and Balancing Delay Using Fanout Tree Buffering and Gate-Sizing," Synthesis and Simulation Meeting and International Interchange, pp. 337-344, Oct. 1993.

44. H.Y. Liou, T.T. Lin, L.T. Liu, and C.K. Cheng, "Circuit Partitioning for Pipelined Pseudo-Exhaustive Testing Using Simulated Annealing," IEEE Custom Integrated Circuits Conf., pp. 417-420, May 1994.

45. L.T. Liu, M. Shih, and C.K. Cheng, "Data Flow Partitioning for Clock Period and Latency Minimization," ACM/IEEE Design Automation Conf., pp. 658-663, June 1994.

46. N.C. Chou, L.T. Liu, C.K. Cheng, W.J. Dai, and R. Lindelof, "Circuit Partitioning for Huge Logic Emulation Systems," ACM/IEEE Design Automation Conf., pp. 244-249, June 1994.

47. J. Chung and C.K. Cheng, "Optimal Buffered Clock Tree Synthesis," IEEE ASIC Conf., pp. 130-133, Sept. 1994.

48. H.Y. Liou, T.T. Lin, and C.K. Cheng, "A Study of Pipelined Pseudo-Exhaustive Testing on VLSI Circuits with Feedback," IEEE ASIC Conf., pp. 421-425, Sept. 1994.

49. J. Chung and C.K. Cheng, "Skew Sensitivity Minimization of Buffered Clock Tree," IEEE ICCAD Conf., pp. 280-283, Nov. 1994.

50. L.T. Liu, M.T. Kuo, C.K. Cheng, and T.C. Hu, "Performance-Driven Partitioning Using A Replication Graph Approach," ACM/IEEE Design Automation Conf., June 1995, pp. 206-210.

51. M.T. Kuo, L.T. Liu, and C.K. Cheng, "Finite State Machine Decomposition for I/O Minimization," IEEE Int. Symp. on Circuits and Systems, pp. 1061-1064, May 1995.

52. J. Lillis, C.K. Cheng, and T.T. Lin, "Optimal and Efficient Buffer Insertion and Wire Sizing," IEEE Custom Integrated Circuits Conf., May 1995, pp. 259-262.

53. J. Chung, D. Kao, C.K. Cheng, and T.T. Lin, "Optimization Of Power Dissipation And Skew Sensitivity In Clock Buffer Synthesis" Int. Symp. on Low Power Design, pp. 179-184, April 1995.

54. J. Li and C.K. Cheng, "Routability Improvement Using Dynamic Interconnect Architecture," IEEE FPGAs for Custom Computing Machines, April 1995.

55. M.T. Kuo, L.T. Liu, and C.K. Cheng, "Finite State Machine Partitioning for I/O Limited Design," Int. Symp. on VLSI Technology, Systems, and Applications, May 1995.

56. R.J. Carragher, M. Fujita, and C.K. Cheng, "Simple Tree-Construction Heuristics for the Fanout Problem," Proc. of the 1995 ACM/IEEE International Workshop on Logic Synthesis, Tahoe City, CA., May 23-26, 1995, pp. 1-11 -- 1-22, International Conference on Computer Design, October 1995.

57. X. Hong, Y. Cai, C. Qiao, P. Huang, Z. Kang, T. Xue, E.S. Kuh, C.K. Cheng, "Tiger: A Timing-Driven Gate Array and Standard Cell Layout System," IEEE Int. Conf. on Solid-State and Integrated Circuit Technology, pp. 338-342, 1995.

58. L.T. Liu, M.T. Kuo, S.C. Huang, and C.K. Cheng "A Gradient Method of the Initial Partition of Fiduccia-Mattheyses Algorithm," IEEE/ACM Int. Conf. on Computer-Aided Design, Nov. 1995, pp. 229-234.

59. J. Li, J. Lillis, and C.K. Cheng, "Linear Decomposition Algorithmm for VLSI Design Applications," IEEE/ACM Int. Conf. on Computer-Aided Design, Nov. 1995, pp. 223-228.

60. J. Lillis, C.K. Cheng, and T.T. Lin, "Optimal Wire Sizing and Buffer Insertion for Low Power and a Generalized Delay Model," IEEE/ACM Int. Conf. on Computer Aided Design, Nov. 1995, pp. 138-143.

61. C.C. Tsai, C.K. Cheng, D.Y. Kao, and T.T. Lin, "Performance Driven Multiple Sources Bus Synthesis Using Buffer Insertion," ASP/DAC Aug. 1995, pp. 273-278, Chiba, Japan.

62. C.K. Cheng, "Rapid Prototyping Systems using Field Programmable Devices," invited paper, VLSI/CAD workshop, Taiwan, Aug. 17-19, 1995.

63. D.Y. Kao, C.C. Tsai, C.K. Cheng, and T.T. Lin, "New Design and Implementation for Singal Repeaters," VLSI/CAD workshop, Taiwan, pp. 173-176, Aug. 17-19, 1995.

64. J. Li, J. Lillis, L.T. Liu, and C.K. Cheng, "New Spectral Linear Placement and Clustering Approach, " ACM/IEEE Design Automation Conf., June 1996, pp. 88-93.

65. M.T. Kuo, L.T. Liu, and C.K. Cheng, " Network Partitioning into Tree Hierarchies, " ACM/IEEE Design Automation Conf., June 1996, pp. 477-482.

66. J. Lillis, C.K. Cheng, T.T. Lin, and C.Y. Ho, " New Performance Driven Routing Techniques with Explicit Area/Delay Tradeoff and Simultaneous Wire Sizing," " ACM/IEEE Design Automation Conf., June 1996, pp. 395-400.

67. H.Y. Liou, T.T. Lin, and C.K. Cheng, " Area Efficient Pipelined Pseudo-Exhaustive Testing with Retiming," " ACM/IEEE Design Automation Conf., June 1996, pp. 274-279.

68. J. Lillis, C.K. Cheng, and T.T. Lin, " Algorithms for Optimal Introduction of Redundant Logic for Timing and Area Optimization, Int. Symp. on Circuits and Systems, 1996.

69. J. Lillis, C.K. Cheng, and T.T. Lin, " Smultaneous Routing and Buffer Insertion for High Performance Interconnect, " IEEE Great Lakes Symp. on VLSI, March 1996, pp. 148-153.

70. M.T. Kuo, Y. Wang, C.K. Cheng, and M. Fujita, " BDD-Based Logic Partitioning for Sequential Circuits, " ASP/DAC Jan. 1997, pp. 607-612, Chiba, Japan.

71. F. Liu, J. Lillis, and C.K. Cheng, " A New Layout-Driven Timing Model for Incremental Layout Optimization, " ASP/DAC Jan. 1997, pp. 127-131, Chiba, Japan.

72. J. Dufour, R. McBride, P. Zhang, and C.K. Cheng, " A Custom Cell Placement Tool, ASP/D" AC Jan. 1997, pp. 271-276, Chiba, Japan.

73. J. Lillis and C.K. Cheng, " Timing Optimization for Multi-Source Nets: Characterization and Optimal Repeater Insertion, " ACM/IEEE Design Automation Conf., pp. 214-219, June 1997.

74. J. Xu, P.N. Guo, and C.K. Cheng " Cluster Refinement for Block Placement, " ACM/IEEE Design Automation Conf., pp. 762-765, June 1997.

75. M.T. Kuo and C.K. Cheng " A New Network Flow Approach for Hierarchical Tree Partitioning, " ACM/IEEE Design Automation Conf., pp. 512-517, June 1997.

76. F.J. Liu, J. Lillis, and C.K. Cheng, " Design and Implementation of a Global Router Based on a New Layout Driven Timing Model with Three Poles, " IEEE Int. Symp. on Circuits and Systems, 1997.

77. J. Xu, P.N. Guo, and C.K. Cheng, " Rectilinear Block Placement using Permutation Pair, " Int. Symp. of Physical Design, April 1998.

78. F.J. Liu and C.K. Cheng, " Extending Moment Computation to 2-Port Circuit Representations, " ACM/IEEE Design Automation Conf., pp. 473-476, June 1998.

79. D. Wang, P. Zhang, C.K. Cheng, and A. Sen, " A Performance-Driven I/O Pin Routing Algorithm, " Asia and South Pacific Design Automation Conf., Hong Kong, Jan. 1999.

80. P.N. Guo, C.K. Cheng, and T. Yoshimura, " An O-Tree Representation of Nonslicing Floorplan and Its Applications, " ACM/IEEE Design Automation Conf., pp. 268-273, June 1999.

81. X. Yang, W. Ku, and C.K. Cheng, " RLC Interconnect Delay Estimation via Moments of Amplitude and Phase Response, " IEEE/ACM Int. Conf. on Computer-Aided Design, Nov. 1999, pp. 208-213.

82. X. Yang, C.K. Cheng, and W. Ku, " A New Efficient Simulation Method for RLC Interconnect via Amplitude and Phase Approximation, " ASP/DAC Jan. 2000, Yokohoma, Japan.

83. Y. Pang, C.K. Cheng, and T. Yoshimura, " An Enhanced Perturbing Algorithm for Floorplan Design using O-tree Representation, " Symp. Physical Design, pp. 168-173, April 2000.

84. Y. Pang, F. Balasa, K.V. Lampaert, and C.K. Cheng, " Block Placement with Symmetry Constraints based on the O-tree Non-Slicing Representation, " IEEE/ACM Design Automation Conf., pp. 464-467, June 2000.

85. C.W. Chang, C.K. Cheng, P. Suaris, and M. Marek-Sadowska, " Fast Post-Placement Rewiring using Easily Detectable Functional Symmetries, " IEEE/ACM Design Automation Conf., pp. 286-289, June 2000.

86. X.D. Yang, C.K. Cheng, W.H. Ku, and R.J. Carragher, " Hurwitz Stable Reduced Order Modeling for RLC Interconnect, " Int. Conf. Computer-Aided Design, Nov. 2000, pp. 222-228.

87. X. Hong, G. Huang, Y. Cai, J. Gu, S. Dong, C.K. Cheng, and J. Gu, " Corner Block List: An Effective and Efficient Topological Representation of Non-Slicing Floorplan, " Int. Conf. Computer-Aided Design, Nov. 2000, pp. 8-12.

88. C.K. Cheng, A.B. Kahng, B. Liu, and D. Stroobandt, " Toward Better Wireload Models in the Presence of Obstacles, " Asia South Pacific Design Automation Conf., Jan. 2001, pp. 527-532.

89. C.K. Cheng, " Timing Closure using Layout Based Design Process, " Second Online Symp. for Electronics Engineers, http://www.techonline.com/osee/, Feb. 2001.

90. B. Yao, H. Chen, C.K. Cheng, and R. Graham, " Revisiting Floorplan Representations, " Int. Symp. on Physical Design, 2001, pp. 138-143.

91. S. Zhou, S. Dong, X. Hong, Y. Cai, J. Gu, and C.K. Cheng " ECBL: An Extended Corner Block List with O(n) Complexity and Solution Space Including Optimum Placement, " Int. Symp. on Physical Design, 2001, pp. 150-155.

92. Y. Pang, K. Lampert, C.K. Cheng, and W. Xie, " Rectilinear Block Packing Using O-tree Representation, " Int. Symp. on Physical Design, 2001, pp. 156-161.

93. Y. Ma, X. Hong, S. Dong, Y. Cai, C.K. Cheng, and J. Gu, " Floorplanning with Abutment Constraints and L-Sahped/T-Shaped Blocks Based on Corner Block List, " ACM/IEEE Design Automation Conf. 2001.

94. Y. Ma, S. Dong, X. Hong, Y. Cai, C.K. Cheng, and J. Gu, "VLSI Floorplanning with Boundary Constraints Based on Corner Block List," Asia South Pacific Design Automation Conf., Jan. 2001, pp. 509-512.

95. Z. Qin, Z. Zhu, and C.K. Cheng, "Efficient Transient Analysis for Large Linear Networks," SASIMI Oct. 2001, pp 293-300.

96. X. Wu, X. Hong, Y. Cai, C.K. Cheng, J. Gu, and W. Dai, "Area Minimization of Power Distribution Network Using Efficient Nonlinear Programming Techniques," Int. Conf. Computer-Aided Design, Nov. 2001.

97. H. Chen, C. Qiao, F. Zhou, and C.K. Cheng, "Refined Single Trunk Tree: A Rectilinear Steiner Tree Generator for Interconnect Prediction," Int. Workshop on System Level Interconnect Prediction, pp. 85-90, April 2002.

98. E.Y. Cheng, F. Zhou, B. Yao, C.K. Cheng, and R. Graham, "Balancing the Interconnect Topology for Arrays of Processors between Cost and Power," IEEE Int. Conf on Computer Design, pp. 30-35, Sept. 2002.

99. H. Chen, B. Yao, F. Zhou, and C.K. Cheng, "Physical Planning of On-Chip Interconnect Architectures," IEEE Int. Conf on Computer Design, pp. 180-186, Sept. 2002.

100. H. Chen, B. Yao, F. Zhou, and C.K. Cheng, "The Y-Architecture: Yet Another On-Chip Interconnect Solution," Asia South Pacific Design Automation Conf., pp. 840-846, Jan. 2003.

101. Z. Qin, and C.K. Cheng, "RCLK-VJ Network Reduction With Hurwitz Polynomial Approximation," Asia South Pacific Design Automation Conf., pp. 283-291, Jan. 2003.

102. S. Chen, X. Hong, S. Dong, Y. Ma, Y. Cai, C.K. Cheng, and J. Gu, "A Buffer Planning Algorithm Based on Dead Space Redistribution," Asia South Pacific Design Automation Conf., pp. 435-438, Jan. 2003.

103. T. Jing, X. Hong, Y. Cai, J. Xu, C.K. Cheng, and J. Gu, "UTACO: A Unified Timing and Congestion Optimization Algorithm for Standard Cell Global Routing," Asia South Pacific Design Automation Conf., pp. 834-839, Jan. 2003.

104. H. Chen, C.K. Cheng, A.B. Kahng, I. Mandoiu, and Q. Wang, "Estimation of Wirelength Reduction for lambda-Geometry vs. Manhattan Placement and Routing," Int. Workshop on System Level Interconnect Prediction, pp. 71-76, April 2003.

105. F. Zhou, E.Y. Cheng, B. Yao, C.K. Cheng, and R. Graham, "A Hierarchical Three-Way Interconnect Architecture for Hexagonal Processors," Int. Workshop on System Level Interconnect Prediction, pp. 133-139, April 2003.

106. Y. Ma, X. Hong, S. Dong, S. Chen, Y. Cai, C.K. Cheng, and J. Gu, "An Integrated Floorplanning with an Efficient Buffer Planning Algorithm," Int. Symp. Physical Design, pp. 136-142, April 2003.

107. Z. Qin and C.K. Cheng, "Realizable Parasitic Reduction Using Generalized Y-Delta Transformation, ACM/IEEE Design Automation Conference, pp. 220-225, June 2003.

108. Z. Zhu, B. Yao, and C.K. Cheng, "Power Network Analysis Using an Adaptive Algebraic Multigrid Approach, ACM/IEEE Design Automation Conference, pp. 105-108, June 2003.

109. H. Chen, C.K. Cheng, N.C. Chou, A.B. Kahng, J.F. MacDonald, P. Suaris, B. Yao, and Z. Zhu, "An Algebraic Multigrid Solver for Analytical Placement with Layout Based Clustering, ACM/IEEE Design Automation Conference, pp. 794-799, June 2003.

110. Y. Ma, X. Hong, S. Dong, S. Chen, Y. Cai, C.K. Cheng, and J. Gu, "Dynamic Global Buffer Planning Optimization Based on Detail Block Locating and Congestion Analysis," ACM/IEEE Design Automation Conference, pp. 806-811, June 2003.

111. J. Liu, S. Zhou, H. Zhu, K.T. Tseng, and C.K. Cheng "Optimal Parallel-Prefix Adders using a Dynamic Programming Algorithm," Int. Workshop on Logic and Synthesis, May 2003, pp. 113-119.

112. H. Chen, C.K. Cheng, A.B. Kahng, I. Mandoiu, and Q. Wang, "The Y-Architecture for On-Chip Interconnect: Analysis and Methodology," IEEE/ACM Int. Conf. on Computer-Aided Design, pp. 13-19, 2003.

113. J. Liu, S. Zhou, H. Zhu, C.K. Cheng "An Algorithmic Approach for Generic Parallel Adders," IEEE/ACM Int. Conf. on Computer-Aided Design, pp. 734-740, 2003.

114. Y. Ma, X. Hong, S. Dong, S. Chen, Y. Cai, C.K. Cheng, and J. Gu, "Buffer Allocation Algorithm with Consideration of Routing Congestion," Asia and South Pacific Design Automation Conf., pp. 621-623, 2004.

115. M. Mori, H. Chen, B. Yao, and C.K. Cheng, "A Multiple Level Network Approach for Clock Skew Minimization with Process Variations," Asia and South Pacific Design Automation Conf., pp. 263-268, 2004.

116. H. Chen, C.K. Cheng, A.B. Kahng, M. Mori, and Q. Wang, "Optimal Planning for Mesh-Based Power Distribution," Asia and South Pacific Design Automation Conf., pp. 444-449, 2004.

117. S. Chen, X. Hong, S. Dong, Y. Ma, Y. Cai, C.K. Cheng, and J. Gu, "A Buffer Planning Algorithm with Congestion Optimization," Asia and South Pacific Design Automation Conf., pp. 615-620, 2004.

118. H. Zhu, R. Graham, and C.K. Cheng, "Constructing Zero-deficiency Parallel Prefix Adder of Minimum Depth," Asia and South Pacific Design Automation Conf., pp. 883-888, 2005.

119. S. Zhou, B. Yao, J. Liu, and C.K. Cheng, "Integrated Algorithmic Logical and Physical Design of Integer Multiplier," Asia and South Pacific Design Automation Conf., pp. 1014-1017, 2005.

120. H. Chen, C.K. Cheng, "A Multi-Level Transmission Line Network Approach for Multi-Giga Hertz Clock Distribution," Asia and South Pacific Design Automation Conf., pp. 103-106, 2005.

121. Z. Zhu, K. Rouz, M. Borah, C.K. Cheng, and E.S. Kuh "Efficient Transient Simulation for Transistor-Level Analysis," Asia and South Pacific Design Automation Conf., 240-243, 2005.

122. Y. Ma, X. Hong, S. Dong, C.K. Cheng, "3D CBL: An Efficient Algorithm for General 3D Packing Problems," Midwest Symp. on Circuits and Systems, pp. 1079-1082, 2005.

123. R. Shi, H. Chen, C.K. Cheng, D. Beckman, and D. Huang, "Layer Count Reduction for Area Array Escape Routing," International Conference and Exhibition on Device Packaging, Scottsdale, Arizona, March 13-16, 2005.

124. B. Yao, L.T. Liu, N.C. Chou, P. Suaris, and C.K. Cheng "Unified Quadratic Programming Approach for Mixed Mode Placement," Int. Symp. on Physical Design, 2005.

125. Y. Hu, H. Chen, Y. Zhu, A.A. Chien, and C.K. Cheng, "Physical Synthesis of Energy-Efficient Networks-on-Chip Through Topology Exploration and Wire Style Optimization," IEEE Inf. Conf. on Computer Design, pp. 111-118 2005.

126. H. Chen, R. Shi, C.K. Cheng, and D.M. Harris, "Surfliner: A Distortionless Electrical Signaling Scheme for Speed of Light On-Chip Communications," IEEE Inf. Conf. on Computer Design, pp. 497-502, 2005.

127. S. Zhou, B. Yao, H. Chen, Y. Zhu, and C.K. Cheng, M. Hutton, "Efficient Static Timing Analysis Using a Unified Framework for False Paths and Multi-Cycle Paths," Asia and South Pacific Design Automation Conf., pp. 73-78, 2006.

128. Z. Zhu, C.K. Cheng, "An Unconditional Stable General Operator Splitting Method for Transistor Level Transient Analysis," Asia and South Pacific Design Automation Conf., pp. 428-433, 2006.

129. Z. Zhou, B. Yao, H. Chen, Y.. Zhu, C.K. Cheng, M. Hutton, T. Collins, S. Srinivasan, N. Chou, P. Suaris, "Improving the Efficiency of Static Timing Analysis with False Paths," IEEE/ACM Int. Conf. on Computer Aided Design, pp. 527-531, 2005.

130. J. Liu, M. Chang, C.K. Cheng, and M. Hutton, "An Iterative Division Algorithm for FPGAs," ACM/SIGDA Int. Symp. on Field-Programmable Gate Arrays, pp. 83-89, 2006.

131. Z. Li, X. Hong, Q. Zhao, S. Zeng, J. Bian, H. Yang, and C.K. Cheng, "Integrating Dyanmic Thermal Via Planning with 3D Floorplanning Algorithm," Symp. on Physical Design, 2006.

132. R. Shi, and C.K. Cheng, Efficient Escape Routing for Hexagonal Array of High Density I/Os. ACM/IEEE Design Automation Conf., pp. 1003-1008, 2006.

133. Y. Hu, Y. Zhu, H. Chen, R. Graham, C.K. Cheng, Communication Latency Aware Low Power NoC Synthesis, ACM/IEEE Design Automation Conf., pp. 574-579, 2006.

134. S. Zhou, Y. Hu, R. Graham, C.K. Cheng, and M. Hutton, "Timing Model Reduction for Hierarchical Timing Analysis," IEEE/ACM ICCAD, pp. 415-422, 2006.

135. R. Wang, R. Shi, and C.K. Cheng, "Layer Minimization of Escape Routing in Area Array Packaging,," IEEE/ACM ICCAD, pp. 815-819, 2006.

136. Y. Zhu, T.L. Chen, W. Zhang, T.P. Jung, J.R. Duann, S. Makeig, and C.K. Cheng, Noninvasive Study of the Human Heart using Independent Component Analysis," IEEE Symp. on Bioinformatics and Bioengineering, pp. 340-347, 2006.

137. H. Zhu, R. Shui, H. Chen, C.K. Cheng, A. Deutsch, G. Katopis, "Distortion Minimization for Packaging Level Interconnects," IEEE Electrical Performance of Electronic Packaging, pp. 175-178, 2006.

138. J. Liu, Y. Zhu, H. Zhu, C.K. Cheng, and J. Lillis, "Optimum Prefix Adders in a Comprehensive Area, Timing and Power Design Space," Asia and South Pacific Design Automation Conf., pp. 609-615, 2007.

139. H. Zhu, Y. Zhu, C.K. Cheng, D. Harris, "An Interconnect-Centric Approach to Cyclic Shifter Design Using Fanout Splitting and Cell Order Optimization," Asia and South Pacific Design Automation Conf., pp. 616-621, 2007.

140. H. Zhu, R. Shi, C.K. Cheng, and H. Chen, "Approaching Speed-of-light Distortionless Communication for On-Chip Interconnect," Asia and South Pacific Design Automation Conf., pp. 684-689, 2007.

141. W. Zhang and C.K. Cheng, "Incremental Power Impedance Optimization Using Vector Fitting Modeling," IEEE Int. Symp. on Circuits and Systems, pp. 2439-2442, 2007.

142. H. Peng and C.K. Cheng, "Fast Transient Simulation of Lossy Transmission Lines," IEEE Int. Symp. on Circuits and Systems, pp. 2706-2709, 2007.

143. L. Zhang, H. Chen, B. Yao, K. Hamilton, C.K. Cheng, "Repeated On-Chip Interconnect Analaysis and Evaluation of Delay, Power, and Bandwidth under Different Design Goals, IEEE Int. Symp. on Quality Electronic Design, pp. 251-256, 2007.

144. Y. Zhu, J. Liu, H. Zhu, C.K. Cheng, "Optimizing Mixed-Radix Ling Adders using Integer Linear Programming," IEEE Int. Workshop on Logic and Synthesis, pp. 75-82, 2007

145. A. Shayan-Arani, Y. Zhu, J.R. Duann, T.P. Jung, S. Makeig, and C.K. Cheng, "Spatial Density Reduction in the Study of the ECG Signal Using Independent Component Analysis," IEEE Int. Conf. of Engineering in Medicine and Biology, pp. 5497, 2007.

146. M. Hashimoto, H. Zhu, C.K. Cheng, "Analytical Eye-diagram Model for On-chip Distortionless Transmission Lines and Its Application to Design Space Exploration," IEEE Custom Integrated Circuits Conf. 2007.

147. W.P. Zhang, L. Zhang, R. Shi, H. Peng, Z. Zhu, L. Chua-Eoan, R. Murgai, T. Shibuya, N. Ito, C.K. Cheng, "Fast Power Network Analysis with Multiple Clock Domains," IEEE Int. Conf. on Computer Design, pp. 456-463, 2007.

148. C.C. Liu, H. Zhu, and C.K. Cheng, "Passive Compensation For High Performance InterChip Communication," IEEE Int. Conf. on Computer Design, pp. 547-552, 2007.

149. Y. Hu, Y. Zhu, M.B. Taylor, C.K. Cheng, "FPGA Global Routing Architecture Optimization Using a Multicommodity FLow Approach," IEEE Int. Conf. on Computer Design, pp. 144-151, 2007.

150. A. Shayan-Arani, Y. Zhu, Y.N. Cheng, C.K. Cheng, S.F. Lin, P.S. Chen, "Exploring Cardioneural Signal from Noninvasive ECG Measurement," IEEE Symp. on Bioinformatics & Bioengineering 2007.

151. H. Zhu, C.K. Cheng, A. Deutsch, and G. Katopis, "Predicting and Optimizing Jitter and Eye-Opening Based on Bitonic Step Response," IEEE Electrical Performance of Electronic Packaging, pp. 155-158, 2007.

152. Y. Zhu, J. Liu, H. Zhu, C.K. Cheng, "Timing-Power Optimization for Mixed-Radix Ling Adders by Integer Linear Programming," ASPDAC, pp. 131-137, 2008.

153. L. Zhang, J. Liu, H. Zhu, C.K. Cheng, M. Hashimoto, "High Performance Current-Mode Differential Logic," IEEE ASPDAC, pp. 720-725, 2008.

154. W.P. Zhang, Y. Zhu, W. Yu, R. Shi, H. Peng, L. Chua-Eoan, R. Murgai, T. Shibuya, N. Ito, and C.K. Cheng, "Finding the Worst Case of Voltage Violation in Multi-Domain Clock Gated Power Network with an Optimization Method" IEEE DATE, pp. 540-547, 2008.

155. L. Zhang, W. Yu, H. Zhu, W. Zhang, C.K. Cheng, "Clock Skew Analysis via Vector-Fitting in Frequency Domain," IEEE Int. Symp. on Quality Electronic Design, pp. 476-479, 2008.

156. L. Zhang, W. Yu, H. Zhu, A. Deutsch, G. Katopis, D. Dreps, E.S. Kuh, and C.K. Cheng, "Low Power Passive Equalizer Optimization using Tritonic Step Response," IEEE/ACM Design Automation Conf., pp. 570-573, 2008.

157. R. Shi, W. Yu, Y. Zhu, C.K. Cheng, and E.S. Kuh, "Efficient and Accurate Eye Diagram Prediction for High Speed Signaling," ACM/IEEE Int. Conf. on Computer-Aided Design, pp. 655-661, 2008.

158. O. He, S. Dong, J. Bian, S. Goto, and C.K. Cheng, "A Novel Fixed-outline Floorplanner with Zero Deadspace for Hierarchical Design," ACM/IEEE Int. Conf. on Computer-Aided Design, pp. 16-23, 2008.

159. Y. Zhu, M. Taylor, S. Baden, and C.K. Cheng, "Advancing Supercomputer Performance Through Interconnect Topology Synthesis," ACM/IEEE Int. Conf. on Computer-Aided Design, pp. 555-558, 2008.

160. Y. Zhang, L. Zhang, M. Hashimoto, C.K. Cheng "On-Chip High Performance Signaling using Passive Compensation," IEEE Int. Conf. on Computer Design, pp. 182-187, 2008.

161. L. Zhang, W. Yu, Y. Zhang, R. Wang, A. Deutsch, G.A. Katopis, D.M. Dreps, J. Buckwalter, E.S. Kuh, and C.K. Cheng, "Low Power Passive Equalizer Design for Computer Memory Links," IEEE Hot Interconnects, Symp. on High Performance Interconnects, pp. 51-56, Aug. 2008.

162. A. Shayan, X. Hu, H. Peng, M. Popovich, W. Zhang, C.K. Cheng, L. Chua-Eoan, X. Chen, "3D Power Distribution Network Co-Design for Nanoscale Stacked Silicon ICs," IEEE Electrical Performance of Electronic Packaging, pp. 11-14, 2008.

163. H. Peng, , K. Rouz, M. Borah, and C.K. Cheng, "Parallel Full-Chip Transient Simulation at Transistor Level," IEEE Electrical Performance of Electronic Packaging, pp. 239-242, 2008.

164. Y. Zhang, L. Zhang, A. Deutsch, G.A. Katopis, D.M. Dreps, J.F. Buckwalter, E.S. Kuh, C.K. Cheng, "On-Chip Bus Signaling Using Passive Compensation," IEEE Electrical Performance of Electronic Packaging, pp. 33-36, 2008.

165. H. Peng and C.K. Cheng, "Parallel Transistor Level Circuit Simulation using Domain Decomposition Methods," IEEE Asia and South Pacific Design Automation Conf., pp. 397-402, 2009.

166. L. Zhang, Y. Zhang, A. A. Tsuchiya, M. Hashimoto, E.S. Kuh, and C.K. Cheng, "High Performance On-Chip Differential Signaling Using Passive Compensation for Global Communication," IEEE Asia and South Pacific Design Automation Conf., pp. 385-390, 2009.

167. W. Zhang, Y. Zhu, W. Yu, A. Shayan, R. Wang, Z. Zhu, C.K. Cheng, "Noise Minimization During Power-Up Stage for a Multi-Domain Power Network," IEEE ASPDAC, pp. 391-396, 2009.

168. S. Zeng, W. Yu, F. Gong, X. Hong, J. Shi, Z. Wang, C.K. Cheng, "Efficient Frequency-Dependent Reluctance for Large-Scale Power/Ground Grid," IEEE Int. Conf. on Solid-State and Integrated-Circuit Technology 2008.

169. T. Weng, Y. Zhu, and C.K. Cheng, "Digital Design and Programmable Logic Boards: Do Students Actually Learn More?" ASEE/IEEE Frontiers in Education Conf., Session S1H-1, pp. 1-6, 2008.

170. A. Shayan-Arani, X. Hu, W.P. Zhang, H. Peng, and C.K. Cheng, "Reliability Aware Through Silicon Via Planning for Nanoscale 3D Stacked ICs," Design Automation and Test in Europe, pp. 288-291, 2009.

171. H. Peng, C.K. Cheng, "Parallel Transistor Level Full-Chip Transient Circuit Simulation," Design Automation and Test in Europe, pp. 304-307, 2009, selected for reprint at EDA Tech Forum, pp. 34-38, June 2009.

172. Y. Zhang, L. Zhang, A. Deutsch, G. Katopis, D. Dreps, E.S. Kuh, and C.K. Cheng, Design Methodology of High Performance On-Chip Global Interconnect Using Terminated Transmission-Line," IEEE Int. Symp. Quality of Electronic Design, pp. 451-458, 2009.

173. A. Shayan, X. Hu, W. Zhang, H. Peng, and C.K. Cheng "Parallel Flow to Analyze the Impact of The Voltage Regulator Model in Nanscale Power Distribution Network," IEEE Int. Symp. Quality of Electronic Design, pp. 576-581, 2009.

174. R. Wang, E.F.Y. Young, and C.K. Cheng, "Representing Topological Structures for 3D Floorplanning," Int. Conf. on Communications, Circuits and Systems,IEEE Catalog Number: CFP09807-CDR, pp. 1098-1102, Milpitas, CA, 2009.

175. X. Hu, W. Zhao, P. Du, Y. Zhang, A. Shayan, C. Pan, A.E. Engin, and C.K. Cheng, "On the Bound of Time-Domain Power Supply Noise Based of Frequency-Domain Target Impedance," ACM/IEEE System Level Interconnect Prediction, pp. 69-76, 2009.

176. W.P. Zhang, W. Yu, X. Hu, A. Shayan, A.E. Engin, and C.K. Cheng "Predicting the Worst-Case Voltage Violation in a 3D Power Network," ACM/IEEE System Level Interconnect Prediction, pp. 93-98, 2009.

177. Y. Zhang, X. Hu, A. Deutsch, A.E. Engin, J.F. Buckwalter, and C.K. Cheng, "Prediction of High-Performance On-Chip Global Interconnection," ACM/IEEE System Level Interconnect Prediction, pp. 61-68, 2009.

178. R. Wang, N.C. Chou, B. Salefski, and C.K. Cheng, "Low Power Gated Bus Synthesis using Shortest-Path Steiner Graph for System-on-Chip Communication," ACM/IEEE Design Automation Conf., pp. 166-171, 2009.

179. R. Wang, E.F.Y. Young, Y. Zhu, F. Chung Graham, R.L. Graham, and C.K. Cheng, "3-D Floorplanning using Labeled Tree and Dual Sequences," ACM Int. Symp. on Physical Design, pp. 54-59, 2008.

180. R. Wang and C.K. Cheng, "Octilinear Redistributive Routing in Bump Arrays," ACM Great Lakes Symp. on VLSI, pp. 191-196, 2009.

181. R. Wang and C.K. Cheng, "On The Complexity of Graph Cuboidal Dual Problems for 3-D Floorplanning of Integrated Circuit Design," ACM Great Lakes Symp. on VLSI, pp. 257-262, 2009.

182. Y. Zhang, J.F. Buckwalter, and C.K. Cheng, "On-Chip Global Clock Distribution using Directional Rotary Traveling-Wave Oscillator," IEEE Electrical Performance of Electronic Packaging and Systems, pp. 251-254, 2009.

183. S. Zeng, W. Yu, W. Zhang, J. Wang, X. Hong, C.K. Cheng, "Efficient Power Network Analysis with Complete Inductive Modeling," IEEE Int. Symp. on Quality of Electronic Design, pp. 770-775, 2009.

184. W.P. Zhang, L. Zhang, A. Shayan, W. Yu, X. Hu, Z. Zhu, E. Engin, and C.K. Cheng, "On-Chip Power Network Optimization with Decoupling Capacitors and Controlled-ESRs," Asia and South Pacific Design Automation Conference, pp. 119-124, 2010.

185. X. Hu, W. Zhao, R. Du, A. Shayan, C.K. Cheng, "An Adaptive Parallel Flow for Power Distribution Network Simulation Using Discrete Fourier Transform," Asia and South Pacific Design Automation Conference, pp. 125-130, 2010.

186. P. Du, X. Hu, S.H. Weng, A. Shayan, X. Chen, E. Engin, and C.K. Cheng "Worst-Case Noise Prediction With Non-zero Current Transition Times for Early Power Distribution System Verification," IEEE Int. Symp. on Quality Electronic Design, pp. 624-631, 2010.

187. Y. Zhang, J.F. Buckwalter, and C.K. Cheng, "Performance Prediction of Throughput-Centric Pipelined Global Interconnects with Voltage Scaling," ACM/IEEE Int. Workshop on System Level Interconnect Prediction, pp. 69-76, 2010.

188. C.K. Cheng, A.B. Kahng, K. Samadi, and A. Shayan, "Worst-Case Performance Prediction Under Supply Voltage and Temperature Variation," ACM/IEEE Int. Workshop on System Level Interconnect Prediction, pp. 91-96, 2010.

189. X. Hu, P. Du, and C.K. Cheng, "Exploring the Rogue Wave Phenomenon in 3D Power Distribution Networks," IEEE Electrical Performance of Electronic Packaging and Systems, pp. 57-60, 2010.

190. Y. Zhang, J.F. Buckwalter, and C.K. Cheng "High-Speed Low-Power On-Chip Global Link Design using Continuous-Time Linear Equalizer," IEEE Electrical Performance of Electronic Packaging and Systems, pp. 5-8, 2010.

191. X. Hu, T. Toms, R. Radojcic, M. Nowak, N. Yu, and C.K. Cheng, "Enabling Power Distribution Network Analysis Flows for 3D ICs," IEEE Int. Conf. on 3D System Integration, pp. 1-4, 2010.

192. O. He, S. Dong, J. Bian, S. Goto, and C.K. Cheng, "Bus Via Reduction based on Floorplan Revising," ACM Great Lakes symp. on VLSI, pp. 9-14, 2010.

193. C.K. Cheng, "Placement and Beyond in Honor of Ernest S. Kuh," ACM Int. Symp. on Physical Design, pp. 5-7, 2011.

194. C.K. Cheng, P. Du, A.B. Kahng, G.K.H. Pang, Y. Wang, and N. Wong, "More Realistic Power Grid Verification Based on Hierarchical Current and Power Constraints," ACM Int. Symp. on Physical Design, pp. 159-166, 2011.

195. S.H. Weng, P. Du, C.K. Cheng, "A Fast and Stable Explicit Integration Method by Matrix Exponential Operator for Large Scale Circuit Simulation," IEEE Int. Symp. on Circuits and Systems, pp. 1467-1470, 2011.

196. A. Shayan, X. Hu, C.K. Cheng, W. Yu, and C. Pan, "Linear Dropout Regulator based Power Distribution Design under Worst Loading," IEEE ASICON, pp. 640-643, 2011.

197. S.H. Weng, Q, Chen, and C.K. Cheng, "Circuit Simulation by Matrix Exponential Method," IEEE ASICON, pp. 462-465, 2011.

198. P. Du, S.H. Weng, X. Hu, and C.K. Cheng, "Power Grid Sizing via Convex Programming," IEEE ASICON, pp. 430-433, 2011.

199. X. Hu, P. Du, and C.K. Cheng, "Exploring 3D Power Distribution Network Physics," IEEE ASICON, pp. 663-666, 2011.

200. C.K. Cheng, P. Du, A.B. Kahng, and S.H. Weng, "Low-Power Gated Bus Synthesis for 3D IC via Rectilinear Shortest-path Steiner Graph," ACM Int. Symp. on Physical Design, pp. 105-112, 2012.

201. P. Du, W. Zhao, S.H. Weng, C.K. Cheng and R. Graham, "Character Design and Stamp Algorithms for Character Projection Electron-Beam Lithography, ASPDAC, pp. 725-730, 2012.

202. G. Sun, S.H. Weng, C.K. Cheng, B. Lin, and L. Zeng, "An On-Chip Global Broadcast Network Design with Equalized Transmission Lines in the 1024-Core Era," IEEE/ACM International Workshop on System Level Interconnect Prediction, 2012.

203. Y.T. Wang, Y. Wang, C.K. Cheng, and T.P. Jung, "Measuring Steady-State Visual Evoked Potential from Non-hair-bearing Areas," IEEE Engineering in Medicine and Biology Conf., pp. 1806-1809, 2012.

204. S.H. Weng, Q.Chen, N. Wong, and C.K. Cheng, "Circuit Simulation using Matrix Exponential Method for Stiffness Handling and Parallel Processing", Int. Conf. on Computer Aided Design, 407-414, 2012.

205. Q. Chen, W. Schoenmaker, S.H. Weng, C.K. Cheng, G.H. Chen, L.J. Jiang, and N. Wong, "A Fast Time-Domain EM-TCAD Coupled Simulation Framework via Matrix Exponential," Int. Conf. on Computer Aided Design, pp. 422-428, 2012 (Best Paper Award Candidate, 5/82 papers/338 submissions).

206. H. Liu and C.K. Cheng, "Untra-Low Power On-Chip Differential Interconnects Using High-Resolution Comparator," IEEE Electrical Performance of Electronic Packaging and Systems, pp. 15-18, 2012.

207. C.C. Chou, H.H. Chuang, T.L. Wu, S.H. Weng, and C.K. Cheng, "Eye Prediction of Digital Driver with Power Distribution Network Noise" IEEE Electrical Performance of Electronic Packaging and Systems, pp. 131-134, 2012 (Best Student Paper Award: 1 out of 104 submissions, 45 oral presentations).

208. Y.K. Ho, X.W. Shih, Y.W. Chang, and C.K. Cheng, "Layer Minimization in Escape Routing for Staggered-Pin-Array PCBs," IEEE ASPDAC, pp. 187-192, 2013.

209. Y. Wang, Y. Jun, C.K. Cheng, and T.P. Jung, "Developing Stimulus Presentation on Mobile Devices for a Truly Portable SSVEP-based BCI," IEEE Engineering in Medicine and Biology Conf., pp. 5271-5274, 2013.

210. L. Huang, X. Huang, Y. Wang, Y. Jun, T.P. Jung and C.K. Cheng, "Empirical Mode Decomposition Improves Detection of SSVEP," IEEE Engineering in Medicine and Biology Conf., pp. 3901-3904, 2013.

211. X. Zhang and C.K. Cheng, "Worst-case Noise Prediction Using Power Network Impedance Profile," ACM/IEEE SLIP, pp. 1-8, 2013.

212. X. Zhang, Y. Liu, R. Coutts, C.K. Cheng, "Power Distribution Network Design Optimization with On-Die Voltage-Dependent Leakage Path," IEEE Conf. on Electrical Performance of Electronic Packaging and Systems, pp. 87-90, 2013.

213. H. Zhuang, S.H. Weng, C.K. Cheng, "Power Grid Simulation using Matrix Exponential Method with Rational Krylov Subspaces," IEEE ASICON, C5-5, 2013.

214. J. Lu, P. Chen, S. Lu, D. Huang, C.C. Teng, and C.K. Cheng, "FFTPL: An Analytic Placement Algorithm Using Fast Fourier Transform for Density Equalization," IEEE ASICON, C5-4, 2013.

215. Y. Wang, Y. Wang, Y. Jun, X. Huang, L. Huang, N. Wong, T.P. Jung, A.J. Mandell, and C.K. Cheng, "Study of Visual Stimulus Waveforms via Forced van der Pol Oscillator Model for SSVEP-Based Brain-Computer Interface," IEEE Int. Conf. on Communications, Circuits and Systems, 2013.

216. H. Su, H. Liu, S.H. Weng, H. Wang, A. Presswala, H. Zhuang, P. Mercier, and C.K. Cheng, "A Non-contact Biopotential Sensing System With Motion Artifact Suppression," IEEE Int. Conf. on Communications, Circuits and Systems, pp. 314-318, 2013.

217. H. Zhuang, J. Lu, K. Samadi, Y. Du, and C.K. Cheng, "Performance-Driven Placement for Design of Rotation and Right Arithmetic Shifters in Monolithic 3D ICs," IEEE Int. Conf. on Communications, Circuits and Systems, pp. 509-513, 2013.

218. Y. Liu, X. Zhang, and C.K. Cheng, "Minimizing the Worst-case Voltage Noise for Power Distribution Network using Time-varying Equivalent Serial Resistance," IEEE Int. Conf. on Communications, Circuits and Systems, pp. 458-462, 2013.

219. I. Kang, X. Wang, J.H. Lin, R. Coutts, and C.K. Cheng, "Impulse Generation from S-Parameters for Power Delivery Network Simulation," IEEE Symp. on Electromagnetic Compatibility and Signal Integrity, pp. 277-281, 2015.

220. H. Zhuang, I. Kang, X. Wang, J.H. Lin, and C.K. Cheng, "Dynamic Analysis of Power Delivery Network with Nonlinear Components Using Matrix Exponential Method," IEEE Symp. on Electromagnetic Compatibility and Signal Integrity, pp. 248-252, 2015.

221. H. Zhuang, S.H. Weng, J.H. Lin, and C.K. Cheng, "MATEX: A Distributed Framework for Transient Simulation of Linear Circuits," ACM/IEEE Design Automation Conf., 2014.

222. J. Lu, P. Chen, C.C. Chang, L. Sha, D. Huang, C.C. Teng, and C.K. Cheng, "An Analytic Nonlinear Algorithm for Mixed-Size Placement," ACM/IEEE Design Automation Conf., 2014 (Best Paper Award Candidate, 12 out of 174 papers, 787 submissions).

223. X. Zhang, J. Lu, Y. Lu, and C.K. Cheng, "Worst-Case Noise Area Prediction of On-Chip Power Distribution Network," IEEE/ACM International Workshop on System Level Interconnect Prediction, 2014.

224. Y.T. Wang, M. Nakanishi, S. Lind Kappel, P. Kidmose, D. Mandic, Y. Wang, C.K. Cheng, T.P. Jung, "Developing an Online Steady-State Visual Evoked Potential-Based Brain-Computer Interface System Using EarEEG," IEEE EMBC 2015.

225. H. Zhuang, W. Yu, I. Kang, X. Wang, and C.K. Cheng, "An Algorithmic Framework for Efficient Large-Scale Circuit Simulation using Exponential Integrators," ACM/IEEE Design Automation Conf., 2015.

226. J.H. Lin, H. Liu, C.H. Liu, P. Lam, G.Y. Pan, H. Zhuang, I. Kang, P.P. Mercier, and C.K. Cheng, "An Interdigital Non-Contact ECG Electrode for Impedance Compensation and Signal Restoration," IEEE Biomedical Circuits and Sysatems, pp. 1-4, 2015.

227. J. Lu, H. Zhuang, I. Kang, P. Chen, and C.K. Cheng, "ePlace-3D: Electrostatics based Placement for 3D-ICs," International Symp. on Physical Design, pp. 1-8, 2016.

228. X. Zhang, R. Coutts, and C.K. Cheng, "Boosting Off-Chip Interconnects Through Power Line Communication," IEEE Electrical Performance of Electronic Packaging and Systems, pp. 189-191, 2016.

229. F. Qiao, I. Kang, D. Kane, F.Y. Young, C.K. Cheng and R. Graham, "3D Floorplan Representations: Corner Links and Partial Order," IEEE Int. Conf. on 3D System Integration (3DIC), pp. 1-5, Nov. 2016.

230. X. Zhang, D. Park, and C.K. Cheng, "Boosting Off-chip Interconnects through Chip-to-Chip Capacitive Coupled Communication" IEEE Electrical Performance of Electronic Packaging and Systems, 2017.

231. I. Kang and C.K. Cheng, "Physical Layout after Half a Century: From Back-Board Ordering to Multi-Dimensional Placement and Beyond," ACM Int. Symp. Physical Design, pp. 123-128, 2017.

232. X. Wang, H. Zhuang, and C.K. Cheng, "Exploring the Exponential Integrators with Krylov Subspace Algorithms for Nonlinear Circuit Simulation," ACM/IEEE Int. Conf. on Computer Aided Design, pp. 163-168, 2017.

233. C.K. Cheng, R. Graham, I. Kang, D. Park, and X. Wang, "Tree Structures and Algorithms for Physical Design," ACM Int. Symp on Physical Design, 2018.

234. I. Kang, D. Park, C. Han, and C.K. Cheng, "Fast and Precise Routability Analysis with Conditional Design Rules," System Level Interconnect Prediction, 2018.

235. P.Y. Hsu, C. Yao, Y. Wang, and C.K. Cheng, "Adaptive Sensitivity Analysis with Nonlinear Power Load Modeling," System Level Interconnect Prediction, 2018.

236. P. Chen, C.K. Cheng, D. Park, and X. Wang, "Transient Circuit Simulation for Differential Algebraic Systems using Matrix Exponential," ACM/IEEE Int. Conf. on Computer Aided Design, p. 99, 2018.

237. D. Park, I. Kang, Y. Kim, S. Gao, B. Lin, and C.K. Cheng, "ROAD: Routability Analysis and Diagnosis Framework Based on SAT Techniques," ACM/IEEE Int. Symp. on Physical Design, pp. 65-72, 2019.

238. E. Chang, C.K. Cheng, A. Gupta, P.H. Hsu, P.Y. Hsu, A. Moffitt, A. Ren, I. Tsaur, and S. Wang, "Cuff-less Blood Pressure Monitoring with a 3-Axis Accelerometer," IEEE EMBC 2019.

239. D. Park, D. Lee, I. Kang, S. Gao, B. Lin, C.K. Cheng, "SP&R: Simultaneous Placement and Routing Framework for Standard Cell Synthesis in Sub-7nm," IEEE Asia and South Pacific Design Automation, pp. 345-350, 2020.

240. P.Y. Hsu, and C.K. Cheng, "Arrhythmia Classification using Deep Learning and Machine Learning with Features Extracted from Waveform-based Signal Processing," IEEE Int. Conf. of Engineering in Medicine & Biology Society (EMBC), pp. 292-295, 2020.

241. P.Y. Hsu, and C.K. Cheng, "R-peak Detection Using a Hybrid of Gaussian and Threshold Sensitivity," IEEE Int. Conf. of Engineering in Medicine & Biology Society (EMBC), pp. 4470-4474, 2020.

242. C.K. Cheng, C. Ho, D. Lee, and D. Park, "A Routability-Driven Complimentary-FET (CFET) Standard Cell Synthesis Framework using SMT," ACM/IEEE Int. Conf. on Computer-Aided Design, pp. 1-8, 2020.

243. C.K. Cheng, C.T. Ho, C. Jiao, X. Wang, Z. Zeng, and X. Zhan, "A Parallel-in-Time Circuit Simulator for Power Delivery Networks with Nonlinear Load Models," IEEE Conf. on Electrical Performance of Electronic Packaging and Systems, pp. 1-3, 2020.

244. C.K. Cheng, D. Lee, and D. Park, "Standard-Cell Scaling Framework with Guaranteed Pin-Accessibility," IEEE Int. Conf. on Circuits and Systems, pp. 1-5, 2020.

245. T.C. Lin, D. Merrill, Y.Y Wu, C. Holtz, and C.K. Cheng, "A Unified Printed Circuit Board Routing Algorithm with Complicated Constraints and Differential Pairs," IEEE Asia and South Pacific Design Automation Conf., pp. 170-175, 2021.

246. C.K. Cheng, D. Lee, B. Lin, A.B. Kahng, I. Kang, M. Kim, D. Park, M. Woo, "CoRe-ECO: Concurrent Refinement of Detailed Place-and-Route for an Efficient ECO Automation," IEEE Int. Conf. on Computer Design, pp. 366-373, 2021.

247. C.K. Cheng, C. Ho, C. Holtz, and B. Lin, "Design and System Technology Co-Optimization Sensitivity Prediction for VLSI Technology Development using Machine Learning," ACM/IEEE Int. Workshop on System-Level Interconnect Pathfinding, pp. 8-15, 2021.

248. U. Mallappa, and C.K. Cheng, "Gra-lpo: Graph Convolution based Leakage Power Optimization," IEEE Asia and South Pacific Design Automation Conference, pp. 697-702.

249. C.K. Cheng, C. Ho, C. Holtz, "Net Separation-Oriented Printed Circuit Board Placement via Margin Maximization," ACM/IEEE Asia and South Pacific Design Automation Conf. pp. 288-293, 2022. Best Paper Award (2 out of 95 papers/310 submissions).

250. P. Chen, A. Chern, C. Holtz, A. Li, Y. Wang, "Placement Initialization via a Projected Eigenvector Algorithm," ACM/IEEE Design Automation, 2022.

251. U. Mallappa, C.K. Cheng, B. Lin, "JARVA: Joint Application-Aware Oblivious Routing and Static Virtual Channel Allocation," IEEE/ACM Int. Symp. on Networks-on-Chip, 2022.