Integrated Circuit Layout Automation
Universityof California, San Diego
- Chung-Kuan Cheng, CSE2130, ckcheng at ucsd.edu, tel: 858 534-6184
- Lectures: 9:30-10:50AM, TuTh, WLH2209
- Combinatorial Algorithms for Integrated Circuit Layout, by T. Lengauer, A Wiley-Teubner Series
OverviewIn the era of nanoscaled technologies, interconnect dominates the system performance and power consumption. We will discuss the impact of physical layout and the approaches to tackle the problems. We will discuss the formulations, optimal solutions, and heuristic approaches. The course is open to students who are interested in hardware architectures, combinatoric algorithms, or computer-aided designs.
Notes and Papers
- ITRS Roadmap and Low Power Design Methodologies Summary, Interconnect, Emerging Devices Lecture 1: Introduction Lecture 2: Roadmap Homework 1: Roadmap
- Partitioning: (1) Two way partitioning, (2) Multiple way partitioning, (3) Multiple level partitioning, (4) Replication cuts, (5) Performance-driven partitioning, (6) Partitioning for FPGAs. Partitioning Tutorial, Lecture 3: Partitioning Homework 2: Partitioning
- Floorplanning: (1) Floorplanning representations, (2) Block configurations, (3) 3D floorplanning. Floorplanning Tutorial Lecture 4: Floorplanning Lecture 4: Floorplanning(2) Homework 3: Relevant Publications
- Placement: (1) Placement algorithms, (2) Local placement, (3) Performance driven placement. Lecture 5: Placement
- Global Routing: (1) Multi-commodity flows, (2) Steiner Trees, (3) Performance driven routing.
- Detail Routing: (1) Channel routing, (2) Maze routing, (3) PC board routing. Lecture 6: Routing
- Special Net Routing: (1) Bus routing, (2) Clock networks, (3) Net matching, (4) Power/Ground distributions. Performance Driven Routing, Shifter: Logic, Placement, and Routing
- Cell Layout, Compaction.