CSE 291 High Performance Interconnect Fall 2012 University of California, San Diego

Course Information

Instructor
• CK Cheng, ckcheng+291@ucsd.edu, 858 534-6184
Schedule
• Lectures: 5:00-6:20PM, TTH, CSE2217
• No class on Tu 10/23 due to IEEE EPEPS conferencce.
References
• High Speed Signal Propagation: Advanced Black Magic Howard Johnson and Martin Graham, Prentice Hall, 2003, and a collection of recent publications.
Content With the advance of microelectronic nanotechnologies, interconnect becomes one dominant factor of system performance, e.g. system on chips, many cores, and terahertz designs. In this course, we discuss the following subjects.
• 1. Overall structure of interconnect and packaging with state of the art examples.
• 2. Electrical and physical scaling according to ITRS roadmaps.
• 3. Interconnect modeling: parasitic extraction, S parameters, wires and transmission lines models, and eye diagram prediction.
• 4. Interconnect signaling: voltage mode and current mode signaling, coding, and scaling effect.
• 5. Transceivers: passive and active equalizers of digital signaling, comparators, and clock recovery.
• 6. Power distribution network: network structures, target impedance, equivalent serial resistance, and rogue wave phenomenon.
• 7. Clock distribution: timing and synchronization, jitters and power dissipation.
• 8. Thermal issues.
Lecture Notes and Papers Homework
• Homework 1 (Due 10/18) Compare Blue Gene/L and z196 in terms of i. computation power, ii. communication latency, iii. communication bandwidth, iv. power efficiency, v. space efficiency. Define and explain your metrics.
• Homework 2 (Due 11/6) Two of the following three questions:
• 1. Digital input vs. power spectrum For a 5Gbps link, change the rise time and plot the power spectrum. Identify the knee frequency.
• 1.1. Try three rise times: 0.1T, 0.4 and 0.8T, where T is the time interval of each bit.
• 1.2 Use three different binary codes for 1.1, e.g. 8b/10b and 64b/66b encodings.
• 2. Prove the Kramers-Kroning relations in chapter 2.
• 3. Update the trends of high performance interconnect and packaging (page 4 in lecture 2) for years 2011, 2015, 2020, and 2025.