Digital Design Systems Labs
Universityof California, San Diego
News & Updates
- 12/01/2010 : [Gopi] Additional Practice Final Exam Questions and solutions as asked by most students in the last discussion of the quarter.ALL THE BEST fellas :)
- 12/01/2010 : [Gopi] Practice Final solution updated
- 11/30/2010 : [Gopi] Lab-4 : Test programs are added. Some demo programs are also given for fun :)
- 11/29/2010 : [Gopi] Lab-4 : We will take demos on Wednesday(12/1), Thursday(12/2) and Friday(12/3). Kindly finish your demos by Friday(12/3). Any late demos would cost you 25% on Monday(12/6) and 50% on Wednesday(12/8). No demos entertained post 12/8 i.e. 0% will be awarded for demos
- 11/29/2010 : [Gopi] Lab-4 : Extra lab hours : Gopi [Thursday 2-4PM + Friday 2-6 PM], Shams [Thursday 1-2PM + Friday 10-1 PM], Vikram [Wednesday 9AM-1PM + Thursday 6-8PM]
- 11/22/2010 : [Vikram] : Please sign up for Lab 3 Demo using the sign up sheet CSE 140L Lab-3 Demo Signup Sheet. Try to distribute yourself evenly among the three days. Your Demos must be done by Monday : November 29th.
- 11/22/2010 : [Vikram] : Extra OH will be held as follows : Vikram : W (Nov 24th : 10 to 1) ; Gopi : T (Nov 23rd : 12.30 to 3.30) ; Shams : M (Nov 29th : 10 to 1).
- 11/21/2010 : [Vikram] : A sample vhdl file for Part 3 Lab 3 demonstrating the use of components (clk_div.vhd) and port mapping can be downloaded here .
- 11/19/2010 : [Gopi] Lab-4 : Tiny Computer Design is uploaded
- 11/18/2010 : [Gopi] OH on 11/19 will be from 12-2PM Kindly note the change
- 11/17/2010 : [CK] Lab3 is due on Wed 11/24/2010
- 11/05/2010 : [Vikram] Lab3 is posted
- 11/04/2010 : [Vikram] Please send all future e-mail communication (questions, clarifications and lab reports) to "email@example.com" instead of mailing any one TA.
- 11/2/2010 : [Shams] Lab-2 Timing Simulation guide: Please follow the steps given in the guide to generate a timing simulation waveform for part-3 and show the critical path. Do not worry about timing simulations for other parts.
- 11/2/2010 : [Gopi] CSE 140L Lab-2 Demo Signup Sheet : Kindly sign-up this sheet for the Lab-2 Demos between 11/8 and 11/12. You are arranged according to the Group Number given to you. This group number stays with you till this quarter end. Co-ordinate and spread yourselves evenly so that the count per demo class shall not shoot beyond 30. Make your choice as Yes/No. We welcome you to give the demo before 11/5 as well.
- 9/30/2010 : [Gopi] Added lab discussion class-1 notes
Objective of this course is to introduce digital components and provide hands-on experience in building digital circuits using computer aided design software. Altera Quartus II program is the primary software tool: https://www.altera.com.
- CK Cheng, CSE2130, firstname.lastname@example.org, 858 534-6184
- Lectures: 5:00-5:50PM, Th, Center 113
- Discussion: 5:00-5:50PM, W, Center 109
- [H] Digital Design and Computer Architecture, David Money Harris and Sarah L. Harris, published by Morgan Kaufmann, 2007
- [S] Introduction to Digital Systems, James Palmer and David Perlman, published by Schaum's ouTlines, McGraw Hill, 1993
Hardware and System
- Altera DE1 Education Kit, Quartus II Web Edition
- Gopi Tummala - email@example.com , Office/Lab hours CSE 3219 Friday 2:00PM to 4:00PM
- Shams Pirani - firstname.lastname@example.org, Office/Lab hours CSE 3219 Monday 10:30AM to 12:30PM
- Vikram Murali - email@example.com, Office/Lab hours CSE 3219 Wednesday 11:00AM to 1:00PM
WebCT for CSE140/L
UCSD students should use their email username and password. Student instructions: http://iwdc.ucsd.edu/password.shtml. Concurrent enrollment (Extension) students are not added automatically. Extension students should obtain a registration token from Extension's student services or the ACMS Help Desk and register for an account.
- Lecture 1: Introduction
- Lecture 2: Opertors
- Lecture 3: Combinational Logic Modules and Timing
- Coverage: H.Chapter 2.
- Lecture 4: Flip-Flops, Shifters and Counters
- Lecture 5: Counters
- Lecture 5.1: Hardware Description Languages
- Lecture 6: Interface and State Assignment
- Lecture 7: Transformation between Mealy and Moore machines
- Lecture 8: Interface and State Assignment
- Introduction to Verilog by P.M. Nyasulu
- Final Exam Questions
- Final Exam Solutions
- Correction in the final solutions: Q4b: CNT = flag' in the case of I1=1 & I0=1
- Q4 Solution update
- SP'09 Final Exam Questions
- SP'09 Final Exam Solutions
- SP'07 Final Exam Questions
- SP'07 Final Exam Solutions
Lab Discussion Notes
- Discussion 1 : Altera's Quartus-II Installation, usage and tutorials
- Discussion 1 : Quartus II Introduction Using Schematic Design
- Discussion 1 : Quartus II Introduction Using Verilog Design
- Discussion 1 : ModelSim Tutorial - Chapters 1 and 3
- Discussion 1 : ModelSim User's Manual - Chapters 1,2,7 and 9
- Report and demonstration guidelines
- Additional resources
- Careful operations on the boards are recommended, since we have burnt DE2 boards for unknown reasons. Do NOT touch the back of a board when it is on power. Always put the board on desk before connecting the power line.
- There will be 4 labs (computer simulations, board demonstration, report write-up).
Work in a group of two. One report per group.
- 1. Combinational Circuit Designs: Lab 1 Assignment Simulation Guide : Altera to Modelsim : Simulation Help
- 2. Sequential Circuit Designs: Lab 2 Assignment
- 3. Design of
Machines: Lab 3 Assignment Finite State
- 4. Tiny Computer Design: Lab 4 Assignment - Design files for download : DE1 and DE2 files for tiny computer design
- Addons to lab4: Additional test programs simple add test program(output: adds 0x5555 with 0x1111 and loops) - Full ISA test program(outputs : ACE if PASS else bAd if FAIL) - Fibonacci test program(1,1,2,3,5,8,d,...) - Some Fun part (Not for evaluation -> Changes are needed in Lab4_de1/de2.v): UCSD and Snake demo programs - Snake demo program(snake-like game using HEX displays) - UCSD test program(displays U C S D on four HEX displays)
· Labs (80%)
· Final (20%) 5:00-5:50PM Th 12/2.