cse240a: Principles of Computer Architecture

Petersen Hall 103
Tuesday & Thursday; 12:30-1:50
Fall, 2007


Steven Swanson
Email: swanson @ cs.ucsd.edu
IM (not email): professorswanson@{AIM, Yahoo!, google talk, MS Messenger}
Office: EBU3B 3212
Office Hours: Tuesday: 2:00-3:00, Friday: 10:00-11:00
UCSD homepage

Teaching Assistant

Sat Garcia
Email: sat @ cs.ucsd.edu
Office: EBU3b B225
Office Hours: Monday: 1:00-2:00; Wednesday: 4:00-5:00

Course discussion board: cse240a. Required reading. Get signed up.

Course Description

Computer processor design is undergoing a revolution. Technology constraints mean that conventional design can no longer satisfy our ever-growing appetite for raw single-threaded performance and the myriad applications it enables. As a result, designers must reevaluate existing techniques and develop new approaches for designing next generation processors.

This course will describe the basics of modern processor operation and the technology trends that necessitate a thorough re-thinking of processor design. Topics include instruction set architecture, pipelining, pipeline hazards, bypassing, dynamic scheduling, branch prediction, out-of-order issue, memory-hierarchy design, advanced cache architectures, and multiprocessor architecture issues.

Text books

Required: Patterson & Hennessy, Computer Architecture: A Quantitative Approach, Patterson & Hennessy, Morgan Kaufmann, 4th Edition
Required: Other assigned readings throughout the quarter.
Optional: Computer Architecture Home Page A collection of useful links about current happenings in the architecture research community


Below is the basic grading scheme. You have the option of using an alternate scheme with 25% final, 15% midterm, 15% homework, and 25% projects. You will automatically select the scheme that gives you the better grade.

Homework/paper summaries 10% Homeworks will be assigned through the course.
Projects 20% There will be two small projects.
Midterm 20% The midterm is on October 25th.
Final 30% The final is on December 14th at 11:30-2:30. It will be cummulative.
Class participation 20% Class participation comprises participation in class meetings and activity on the class bulletin board.


Items in the schedule more that one week in the future are subject to change. Check back for updates for the assigned readings, etc. The date for the midterm will not change, however. Nor will deadlines for homeworks/projecsts that have been assigned be move earlier.

I will post the slides for most lectures. Since the slides contain material I am not allowed to distribute publically, they are only available from on campus or via the campus proxy. Instructions for setting up the proxy can be found here. Using the proxy is useful in general, since it gives you full access to the libraries and other resources from off campus.

Date Topic Readings Slides Due Notes
Thursday, September 27 Administrivia; Overview of architecture Appendix A.1 if your architecture is rusty. slides
Tuesday, October 2 CMOS, Technology Scaling A.1, Ch. 1.1-1.12 slides Assignment 1- 1;
Thursday, October 4 Measuring performance, and introduction to caching C.1-C.3, except pages 20-21 slides , slides
Tuesday, October 9 Advanced caching 5.1-5.2 slides Summary 1;
Thursday, October 11 Really advanced caching slides
Tuesday, October 16 Virtual Memory C.4 slides , slides Assignment 2;
Thursday, October 18 No class Summary 2;
Tuesday, October 23 Canceled due to fires
Thursday, October 25 Canceled due to fires
Tuesday, October 30 VM C.5-C.7, 315-317 slides Project 1- 1; Project 1- 2;
Thursday, November 1 Midterm
Tuesday, November 6 ISA A.2-A.4 slides
Thursday, November 8 Pipelining A.5-A.9 slides
Tuesday, November 13 Branch prediction/exceptions/multi-cycle instructions 2.3, 121-125 slides Assignment 3;
Thursday, November 15 Introduction to ILP 2.1-2.2,2.4-2.6, 2.8, 2.10 slides , slides , slides
Tuesday, November 20 Tomasulo's Algorithm Tomasulo Handout
Tomasulo Diagram
Tuesday, November 27 Case Study: Alpha 21264 Alpha 21264 Description slides
Thursday, November 29 Introduction to TLP/Simultaneous multi-threading/Chip multi-processors 3.5,4.1-4.3 slides
Tuesday, December 4 No class Project 2;
Thursday, December 6 multi-processors 4.4-4.10 slides
Friday, December 14 Final Exam Assignment 4- 1; Assignment 4- 2; 11:30-2:30


Assignment 1: Log into and use the class discussion board
Assignment 2: Caching
Assignment 3: Virtual Memory and Basic Pipelining
Assignment 4: End of the Term Pseudo-Assignment

Paper Summaries

Paper 1: Early Computers
Paper 2: Reducing memory latency via non-blocking and prefetching caches


Project 1: Cache Simulator
Project 2: Prefetching competition