Homework Assignments:

• HW #1 -- Due October 5
• P&H 2.3, 2.4, 2.8, 2.15, 2.33, 2.34, 2.37 (just rows 1,4,7,10)
• HW #2 -- Due October 14
  • P&H 4.1, 4.2, 4.7, 4.9, 4.11, 4.17, 4.22, 4.46, 3.2, 3.5, 3.7, 3.10
• HW #3 -- Due October 26
• P&H 5.2 a,b,c, 5.3 d,e,f, 5.8, 5.36*, 5.41, P1
• * use the following frequencies (loads 26%, stores 11%, reg-reg ALU 44%, branch 16%, jump 3%)
• P1 -- same as 5.41, but implement addi
• these might be useful, fig 5.17, fig 5.28, and fig 5.38.
• HW #4 -- Due November 9
  • P&H 6.1, 6.3, 6.4, P2, 6.13, W1 (you can write by hand on figures when you need to).
  • P2 -- using figure 6.41 as a template, highlight all data paths active (active means carrying data that will actually be used to complete the instruction) for the following code, in the cycle that the lw is in the wb stage:
    • lw $5, 1000($4)
    • add $1, $3, $5
    • sw $10, 1004($4)
    • sub $3, $10, $1
  • W1 (web assignment 1):  Give the number of pipeline stages in the integer pipeline for the following machines:  Pentium III, Pentium 4, Alpha 21264, Itanium 2.
• HW #5 -- Due November 23
  • P&H 6.14 (use figure 6.32, not 6.30, but also refer to 6.27 for the control signals), 6.18, P3, P4, 6.21 (for b, consider all forwarding, including reg-file), 6.36
    • P3 -- (a) assuming the following code runs for a very long time, with the branch always taken, what is the CPI?  Assume the base pipelined machine with forwarding, and a branch delay slot.  In calculating CPI, do not count the nop as an instruction.

      • loop:  add $4, $3, $2
      • lw $2, 1000($4)
      • addi $2, $2, #12
      • sub $10, $10, 1
      • beq $2, $10, loop:
      • nop

      • (b) Reorder the code to improve performance and give the new CPI.
    • P4 -- Consider the sequence lw $4, 1000($5), sw $4, 2000($6).  In the best case, should this case require stalling?  Forwarding?  Does our base machine contain the forwarding paths to make this work?  (Hint, figs 6.36 and 6.41 don't even have the sw datapaths -- see fig 6.33 for the sw datapath you should assume is also in 6.36 and 6.41).  If not, briefly describe how it might work.  Do these same issues arise if the 2nd instruction is sw $6, 2000($4)?
• HW #6 -- Due December 2
  • P&H 7.3, 7.9, 7.10 (even if you turned them in already with hw 5), 7.12, 7.23, 7.25, 7.29, 7.33, 7.35, W2.
    • W2:  What are the on-chip cache configurations (size, associativity, block size if you can get it) for the following CPUs?:  Alpha 21264, Itanium 2,  Pentium 4 (if it varies by particular version, just tell us which version).

Note, the homework may include some problems on the CD and not in the book, and even include some problems ("For More Practice" from the CD) for which they make the solutions readily available. For those ("for more practice") problems only, you may consult the answers, but please do so only after solving them (then you can go back and correct).


Very approximate Reading and Exam Schedule:
 

Date	Topic	Critical	Important	Informative
Sept 23	Introduction	1.2	-	1.1, 1.3, 1.4
Sept 28	ISA	2.1-2.6,2.9	2.13,2.15,2.16	2.7,2.8,2.10-2.12
Sept 30	ISA	-	-	-
Oct 5	Performance	4.1-4.3,4.5	4.4	-
Oct 7	Computer Arithmetic	3.1-3.4,B.5		B.6
Oct 12		3.5-3.6	3.8	3.7
Oct 14	Single-Cycle CPU	5.1,5.3,5.4	5.2
Oct 19	Single-Cycle CPU Control, Multi-cycle CPU	5.5		C.3
Oct 21	Microprogramming and Exceptions	5.6		5.7
Oct 26	Pipelining	6.1,6.2
Oct 28	Data Hazards	6.4,6.5
Nov 2
Nov 4	Midterm
Nov 9	Control Hazards	6.6		6.8
Nov 11	Advanced Pipelining	6.9, 6.10
Nov 16	Cache Basics	7.1-7.2
Nov 18	Better Caches	7.3, 7.5	7.6
Nov 23
Nov 25	Thanksgiving
Nov 30
Dec 2
Dec 9	Final Exam, Center Hall 115, 11:30 - 2:30