Dean Tullsen's Publications

Research Interests -- Computer architecture, simultaneous (and other) mulithreading processors, chip multiprocessing, instruction-level parallelism of all kinds, software and hardware techniques for parallel speedup of serial code, low-power and energy-efficient processor architectures...

Dean Tullsen's home page.


Book

Multithreading Architecture, Mario Nemirovsky and Dean M. Tullsen, Morgan & Claypool Publishers, 2012.

Everything Else

http://ieeexplore.ieee.org/document/7950876/

Thermal Time Shifting: Decreasing Data Center Cooling Costs with Phase-Change Materials, Matt Skach, Manish Arora, Chang-Hong Hsu, Qi Li, Dean M. Tullsen, Lingjia Tang, Jason Mars, In IEEE Internet Computing, vol. 21, Iss. 4, July-August, 2017.

Prime+Abort: A Timer-Free High-Precision L3 Cache Attack using Intel TSX, Craig Disselkoen, David Kohlbrenner, Leo Porter, Dean M. Tullsen, In USENIX Security Symposium, August, 2017.

Compiler Techniques to Reduce the Synchronization Overhead of GPU Redundant Multithreading, Manish Gupta, Daniel Lowell, John Kalamatianos, Steven Raasch, Vilas Sridharan, Dean Tullsen, Rajesh Gupta, In the Design Automation Conference, June, 2017.

MemPod: A Clustered Architecture for Efficient and Scalable Migration in Flat Address Space Multi-level Memories, Andreas Prodromou, Mitesh R. Meswani, Nuwan Jayasena, Gabriel H. Loh, Dean M. Tullsen, In 23rd International Symposium on High Performance Computer Architecture, February, 2017.

Reliability and Performance Trade-off Study of Heterogeneous Memories, Manish Gupta, David Roberts, Mitesh R. Meswani, Vilas Sridharan, Dean M. Tullsen, Rajesh K. Gupta, In The International Symposium on Memory Systems, October, 2016.

Horton Tables: Fast Hash Tables for In-Memory Data-Intensive Computing, Alex D. Breslow, Dong Ping Zhang, Joseph L. Greathouse, Nuwan Jayasena, Dean M. Tullsen, In USENIX Annual Technical Conference, July, 2016.

HIPStR: Heterogeneous-ISA Program State Relocation, Ashish Venkat, Sriskanda Shamasunder, Hovav Shacham, Dean M. Tullsen, In 21st International Conference on Architectural Support for Programming Languages and Operating Systems, April, 2016.

The CRISP Performance Model for Dynamic Voltage and Frequency Scaling in a GPGPU, Rajib Nath and Dean M. Tullsen, In International Symposium on Microarchitecture, December, 2015.

Thermal time shifting: leveraging phase change materials to reduce cooling costs in warehouse-scale computers, Matt Skach, Manish Arora, Chang-Hong Hsu, Qi Li, Dean M. Tullsen, Lingjia Tang, Jason Mars: In 42nd International Symposium on Computer Architecture, June, 2015.

Understanding idle behavior and power gating mechanisms in the context of modern benchmarks on CPU-GPU Integrated systems, Manish Arora, Srilatha Manne, Indrani Paul, Nuwan Jayasena, Dean M. Tullsen, In 21st International Symposium on High Performance Computer Architecture, February, 2015.

Harnessing ISA diversity: Design of a heterogeneous-ISA chip multiprocessor, Ashish Venkat and Dean M. Tullsen, In 41st International Symposium on Computer Architecture, June, 2014.

Modeling and analysis of Phase Change Materials for efficient thermal management, Fulya Kaplan, Charlie De Vivero, Samuel Howes, Manish Arora, Houman Homayoun, Wayne Burleson, Dean M. Tullsen, Ayse Kivilcim Coskun, In International Conference on Computer Design, October, 2014.

Enabling Dynamic Heterogeneity Through Core-on-Core Stacking, Vasileios Kontorinis, Mohammad K. Tavana, Mohammad H. Hajkazemi, Dean M. Tullsen, Houman Homayoun in Proceedings of the The 51st Annual Design Automation Conference, 2014

CDTT: Compiler-generated data-triggered threads, Hung-Wei Tseng and Dean M. Tullsen, In 20th International Symposium on High Performance Computer Architecture, February, 2014.

Resistive Computation: A Critique Hamid Mahmoodi, Sridevi Srinivasan Lakshmipuram, Manish Arora, Yashar Asgarieh, Houman Homayoun, Bill Lin, Dean M. Tullsen, in Computer Architecture Letters 13(2), 2014

A comparison of core power gating strategies implemented in modern hardware, Manish Arora, Srilatha Manne, Yasuko Eckert, Indrani Paul, Nuwan Jayasena, Dean Tullsen, in 2014 ACM International Conference on Measurement and Modeling of Computer Systems (SIGMETRICS) , 2014

Load-balanced pipeline parallelism, Md Karmruzzaman, Steven Swanson, Dean M. Tullsen, In SC13, November, 2013.

Thread Row Buffers: Improving Memory Performance Isolation and Throughput in Multiprogrammed Environments, Enric Herrero, Jose Gonzalez, Ramon Canal, Dean M. Tullsen, In IEEE Transactions on Computers, vol. 62, Iss. 9, September, 2013.

The Case for Colocation of HPC Workloads., Alex D. Breslow, Leo Porter, Ananta Tiwari, Michael A. Laurenzano, Laura Carrington, Dean M. Tullsen, and Allan E. Snavely, In Concurrency and Computation: Practice and Experience: Special issue on the Analysis of Performance and Power for Highly Parallel Systems, 2013.

Low-Current Probabilistic Writes for Power-Efficient MRAM Caches, Nikolaos Strikos, Vasileios Kontorinis, Xiangyu Dong, Houman Homayoun, and Dean M. Tullsen, In 2013 International Conference on Computer Design, October, 2013.

REMEDIATE: A scalable fault-tolerant architecture for low-power NUCA cache in tiled CMPs, Abbas Banaiyan, Houman Homayoun, Vasileios Kontorinis, Dean Tullsen, Nikil Dutt In International Conference on Green Computing, June, 2013.

The McPAT Framework for Multicore and Manycore Architectures: Simultaneously Modeling Power, Area, and Timing Sheng Li, Jung Ho Ahn, Richard D. Strong, Jay B. Brockman, Dean M. Tullsen, Norman P. Jouppi
ACM Transactions on Architecture and Code Optimization (TACO), Volume 10, No. 1, April 2013

Redefining the Role of the CPU in the Era of CPU-GPU Integration, Manish Arora, Siddhartha Nath, Subhra Mazumdar, Scott B. Baden, and Dean M. Tullsen, IEEE Micro, Volume 32, No. 6, November, 2012.

Themis: Energy Efficient Management of Workloads in Virtualized Data Centers , Gaurav Dhiman, Vasileios Kontorinis, Raid Ayoub, Liuyi Zhang, Chris Sadler, Dean Tullsen, Tajana Simunic Rosing, In Euro-Par Parallel Processing Workshops, 2013.

Underclocked Software Prefetching: More Cores, Less Energy, Md Kamruzzaman, Steven Swanson, and Dean M. Tullsen, IEEE Micro, Volume 32, No. 4, 2012.

Software Data-Triggered Threads, Hung-Wei Tseng and Dean Michael Tullsen, In Proceedings of the ACM International Ionference on Object Oriented Programming Systems Languages and Applications, October, 2012.

Coalition Threading: Combining Traditional and Non-Traditional Parallelism to Maximize Scalability, Md Kamruzzaman, Steven Swanson, Dean M. Tullsen In Proceedings of the 21st international conference on Parallel Architectures and Compilation Techniques,  September, 2012

Efficient System Design using the Statistical Analysis of Architectural Bottlenecks Methodology, Manish Arora, Feng Wang, Bob Rychlik, and Dean M. Tullsen, In 12th International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation,, July, 2012.

Fast cost efficient designs by building upon the plackett and burman method Manish Arora, Feng Wang, Bob Rychlik, Dean Tullsen, In SIGMETRICS '12 Proceedings of the 12th ACM SIGMETRICS/PERFORMANCE joint international conference on Measurement and Modeling of Computer Systems, June, 2012.

Managing Distributed UPS Energy for Effective Power Capping in Data Centers, Vasileios Kontorinis, Liuyi Eric Zhang, Baris Aksanli, Jack Sampson, Houman Homayoun, Eddie Pettis, Dean M. Tullsen, Tajana Simunic Rosing, In 39th International Symposium on Computer Architecture, June, 2012. You can find the related TCO spreadsheet. You can also read the related battery models tech report.

Eliminating Redundant Computation and Exposing Parallelism Through Data-Triggered Threads, Hung-Wei Tseng and Dean M. Tullsen, IEEE Micro, Special Issue on the Top Picks from the Computer Architecture Conferences, Volume 32, Number 3, 2012.

Hot Peripheral Thermal Management to Mitigate Cache Temperature Variation, Houman Homayoun, Mehryar Rahmatian, Vasileios Kontorinis, Shahin Golshan, and Dean M. Tullsen, In 2012 International Symposium on Quality in Electronic Design, March, 2012.

Execution migration in a heterogeneous-ISA chip multiprocessor, Matthew DeVuyst, Ashish Venkat, Dean M. Tullsen, In 17th International Conference on Architectural Support for Programming Languages and Operating Systems, March, 2012.

Dynamically Heterogeneous Cores Through 3D Resource Pooling, Houman Homayoun, Vasileios Kontorinis, Amirali Shayan, Ta-Wei Lin, and Dean M. Tullsen, In 18th International Symposium on High Performance Computer Architecture, February, 2012.

Data Layout for Cache Performance on a Multithreaded Architecture, Subhradyuti Sarkar and Dean M. Tullsen, In Transactioni on High-Performance Embedded Architectures and Compilers, Volume 3, April, 2011.

Inter-core prefetching for multicore processors using migrating helper threads, Md Kamruzzaman, Steven Swanson, Dean M. Tullsen, In 16th International Conference on Architectural Support for Programming Languages and Operating Systems, March, 2011.

Data-Triggered Threads: Eliminating Redundant Computation, Hung-Wei Tseng and Dean M. Tullsen, In 17th International Symposium on High Performance Computer Architecture, February, 2011. Nominated for Best Student Paper.

Fast Thread Migration via Cache Working Set Prediction, Jeffery A. Brown, Leo Porter and Dean M. Tullsen, In 17th International Symposium on High Performance Computer Architecture, February, 2011. Best Student Paper!

Runtime parallelization of legacy code on a transactional memory system, Matthew DeVuyst, Dean M. Tullsen, Seon Wook Kim, In 6th International Conference on High-Performance and Embedded Architectures and Compilers, January 2011.

Inter-Socket Victim Cacheing for Platform Power Reduction, Subhra Mazumdar, Dean M. Tullsen, and Justin Song, In 2010 International Conference on Computer Design, October, 2010.

Dynamic workload characterization for power efficient scheduling on CMP systems, Gaurav Dhiman, Vasileios Kontorinis, Dean Tullsen, Tajana Rosing, Eric Saxe, Jonathan Chew, In 2010 International Symposium on Low Power Electronics and Design, August, 2010.

Software data spreading: leveraging distributed caches to improve single thread performance, Md Kamruzzaman, Steven Swanson, Dean M. Tullsen, In 2010 Conference on Programning Language Design and Implementation, June, 2010.

Reducing Peak Power with a Table-Driven Adaptive Processor Core, Vasileios Kontorinis, Amirali Shayan, Dean M. Tullsen, Rakesh Kumar, in 42nd International Symposium on Microarchitecture, December, 2009.

McPAT: An Integrated Power, Area, and Timing Modeling Framework for Multicore and Manycore Architectures, Sheng Li, Jung Ho Ahn, Richard D. Strong, Jay B. Brockman, Dean M. Tullsen, Norman P. Jouppi, in 42nd International Symposium on Microarchitecture, December, 2009.

Mapping Out a Path from Hardware Transactional Memory to Speculative Multithreading, Leo Porter, Bumyong Choi, Dean M. Tullsen, in 18th International Conference on Parallel Architectures and Compilation Techniques, September, 2009.

Evaluating the Impact of Job Scheduling and Power Management on Processor Lifetime for Chip Multiprocessors, Ayse K. Coskun, Richard Strong, Dean M. Tullsen, Tajana Simunic Rosing, in 2009 ACM Sigmetrics/Performance, June, 2009.

Creating Artificial Global History to Improve Branch Prediction Accuracy, Leo Porter, Dean M. Tullsen, In Twenty-Third International Conference on Supercomputing, June, 2009.

Fast Switching of Threads Between Cores, Richard Strong, Jayaram Mudigonda, Jeffrey C. Mogul, Nathan Binkert, Dean Tullsen, In ACM SIGOPS Operating Systems Review, Volume 43, Issue 2 , Special Issue on Interactions Among Operating Systems, Compilers, and Multicore Processors, April, 2009.

Mitosis: A Speculative Multithreaded Processor Based on Precomputation Slices, Carlos Madriles, Carlos García Quiñones, Jesús Sánchez, Pedro Marcuello, Antonio González, Dean M. Tullsen, Hong Wang, and John P. Shen, In IEEE Transactions on Parallel and Distributed Systems, Volume 19, Number 7, July, 2008.

The Shared-Thread Multiprocessor, Jeffery A. Brown, Dean M. Tullsen, In 22nd ACM International Conference on Supercomputing, June, 2008.

Accurate Branch Prediction for Short Threads, Bumyong Choi, Leo Porter, Dean M. Tullsen, In Thirteenth International Conference on Architectural Support for Programming Languages and Operating Systems, April, 2008.

Compiler Techniques for Reducing Data Cache Miss Rate on a Multithreaded Architecture, Subhradyuti Sarkar and Dean M. Tullsen, In 2008 International Conference on High Performance Embedded Architectures & Compilers, January, 2008. Also, LNCS vol. 4917.

"The Architecture of Efficient Multi-Core Processors: A Holistic Approach", Rakesh Kumar and Dean M. Tullsen, In Advances in Computers, Volume 69 (M. Zelkowitz, Ed.), Academic Press, 2007, pp. 1-87.

Proximity-Aware Directory-Based Coherence for Multi-core Processor Architectures Jeffery A. Brown, Rakesh Kumar, Dean Tullsen, In 19th ACM Symposium on Parallelism in Algorithms and Architectures, June, 2007.

Accelerating and Adapting Precomputation Threads for Efficient Prefetching, Weifeng Zhang, Dean M. Tullsen, Brad Calder, In 13th International Symposium on High Performance Computer Architecture, January, 2007.

Dynamic Code Value Specialization Using the Trace Cache Fill Unit, Weifeng Zhang, Steve Checkoway, Brad Calder, and Dean M. Tullsen, In 24th International Conference on Computer Design, October, 2006.

Application-Specific Customization of Parameterized FPGA Soft-Core Processors, David Sheldon, Rakesh Kumar, Roman Lysecky, Frank Vahid, Dean Tullsen, In 2006 International Conference on Computer-Aided Design, November, 2006.

Conjoining Soft-Core FPGA Processors, David Sheldon, Rakesh Kumar, Frank Vahid, Dean Tullsen, Roman Lysecky, In 2006 International Conference on Computer-Aided Design, November, 2006.

Core Architecture Optimization for Heterogeneous Chip Multiprocessors, Rakesh Kumar, Dean M. Tullsen, Norman P. Jouppi, In 15th International Symposium on Parallel Architecture and Compilation Techniques, September, 2006.

Exploiting Unbalanced Thread Scheduling for Energy and Performance on a CMP of SMT Processors, Matthew DeVuyst, Rakesh Kumar, and Dean M. Tullsen, In 2006 IEEE International Parallel and Distributed Processing Symposium, April, 2006.

A Self-Repairing Prefetcher in an Event-Driven Dynamic Optimization Framework, Weifeng Zhang, Brad Calder, and Dean M. Tullsen, In 4th International Symposium on Code Generation and Optimization (CGO), March, 2006.

Heterogeneous Chip Multiprocessing, Rakesh Kumar, Dean M. Tullsen, Norman P. Jouppi, and Parthasarathy Ranganathan, IEEE Computer, November 2005, pp. 32-38.

An Event-Driven Multithreaded Dynamic Optimization Framework, Weifeng Zhang, Brad Calder, and Dean M. Tullsen, In 2005 International Conference on Parallel Archtectures and Compilation Techniques, September, 2005.

Mitosis Compiler: An Infrastructure for Speculative Threading Based on Pre-Computation Slices, Carlos García Quiñones, Carlos Madriles, Jesús Sánchez, Pedro Marcuello, Antonio González, Dean M. Tullsen In 2005 Conference on Programning Language Design and Implementation, June, 2005.

Interconnections in Multi-Core Architectures: Understanding Mechanisms, Overheads and Scaling, Rakesh Kumar, Victor Zyuban, Dean M. Tullsen In 32nd International Symposium on Computer Architecture, June, 2005.

A Tree Based Router Search Engine Architecture with Single Port Memories, Florin Baboescu, Dean M. Tullsen, Grigore Rosu, Sumeet Singh In 11th International Symposium on High Performance Computer Architecture, February, 2005.

Architecture-Level Power Optimizations -- What Are the Limits?, John S. Seng, Dean M. Tullsen, Journal of Instruction Level Parallelism, 7 (2005), January, 2005.

The Danger of Interval-Based Power Efficiency Metrics: When Worst Is Best, Yiannakis Sazeides, Rakesh Kumar, Dean M. Tullsen, Theofanis Constantinou, In Computer Architecture Letters, Volume 4, January, 2005.

Control Flow Optimizations Via Dynamic Reconvergence Prediction, Jamison D. Collins, Dean M. Tullsen, Hong Wang, In 37th International Symposium on Microarchitecture, December, 2004.

Balanced Multithreading:  Increasing Throughput Via a Low Cost Multithreading Hierarchy, Eric Tune, Rakesh Kumar, Dean M. Tullsen, Brad Calder, In 37th International Symposium on Microarchitecture, December, 2004.

Conjoined-Core Chip Multiprocessing, Rakesh Kumar, Norman P. Jouppi, Dean M. Tullsen, In 37th International Symposium on Microarchitecture, December, 2004.

Single-ISA Heterogeneous Multi-Core Architectures for Multithreaded Workload Performance, Rakesh Kumar, Dean M. Tullsen, Parthasarathy Ranganathan, Norman P. Jouppi, Keith I. Farkas, In 31st International Symposium on Computer Architecture, June, 2004.

Clustered Multithreaded Architectures -- Pursuing Both IPC and Cycle Time, Jamison D. Collins, Dean M. Tullsen, In 18th International Parallel and Distributed Processing Symposium, April, 2004.

Single-ISA Heterogeneous Multi-Core Architectures: The Potential for Processor Power Reduction, Rakesh Kumar, Keith Farkas, Norm P. Jouppi, Partha Ranganathan, Dean M. Tullsen, In 36th International Symposium on Microarchitecture, December, 2003.

Exploring the Potential of Architecture-Level Power Optimizations, John S. Seng, Dean M. Tullsen, In Third International Workshop on Power-Aware Computer Systems, December, 2003.  Also published in Lecture Notes in Computer Science, Volume 3164, December, 2004.

Initial Observations of a Simultaneous Multithreading Processor, Nathan Tuck, Dean M. Tullsen, In Twelfth International Conference on Parallel Architectures and Compilation Techniques, September, 2003.

A Multi-Core Approach to Addressing the Energy-Complexity Problem in Microprocessors, Rakesh Kumar, Keith Farkas, Norm P. Jouppi, Partha Ranganathan, Dean M. Tullsen, In 2003 Workshop on Complexity-Effective Design, June, 2003.

Processor Power Reduction Via Single-ISA Heterogeneous Multi-Core Architectures, Rakesh Kumar, Keith Farkas, Norm P. Jouppi, Partha Ranganathan, Dean M. Tullsen, Computer Architecture Letters, Volume 2, Apr. 2003

The Effect of Compiler Optimizations on Pentium 4 Power Consumption, John S. Seng, Dean M. Tullsen, In the 7th Annual Workshop on Interaction between Compilers and Computer Architectures, February, 2003

Pointer-Cache Assisted Prefetching, Jamison Collins, Suleyman Sair, Brad Calder, and Dean Tullsen, In 35th Annual International Symposium on Microarchitecture, November 2002.

Compiling for Instruction Cache Performance on a Multithreaded Architecture, Rakesh Kumar, Dean M. Tullsen, In 35th Annual International Symposium on Microarchitecture, November 2002.

Quantifying Instruction Criticality, Eric Tune, Dean Tullsen, and Brad Calder, In Eleventh International Conference on Parallel Architectures and Compilation Techniques, September 2002.

Symbiotic Jobscheduling with Priorities for a Simultaneous Multithreading Processor, Allan Snavely, Dean M. Tullsen, Geoff Voelker, In 2001 International Conference on Measurement and Modeling of Computer Systems (Sigmetrics 02), June, 2002.

Dynamic Speculative Precomputation, Jamison D. Collins,  Dean M. Tullsen, Hong Wang, John P. Shen, In 34th Annual International Symposium on Microarchitecture, December, 2001 (see abstract).

Reducing Power with Dynamic Critical Path Information, John S. Seng, Eric S. Tune,  Dean M. Tullsen, In 34th Annual International Symposium on Microarchitecture, December, 2001 (see abstract).

Handling Long-Latency Loads in a Simultaneous Multithreading Processor, Dean M. Tullsen, Jeff A. Brown, In 34th Annual International Symposium on Microarchitecture, December, 2001 (see abstract).

Runtime Identification of Cache Conflict Misses: The Adaptive Miss Buffer, Jamison D. Collins, Dean M. Tullsen, ACM Transactions on Computer Systems (TOCS), Volume 19, Issue 4, November, 2001.

Speculative Precomputation: Long-range Prefetching of Delinquent Loads, Jamison D. Collins, Hong Wang, Dean M. Tullsen, Christopher Hughes, Yong-Fong Lee, Dan Lavery, John P. Shen In 28th International Symposium on Computer Architecture, July, 2001.

Dynamic Prediction of Critical Path Instructions, Eric Tune, Dongning Liang, Dean M. Tullsen, Brad Calder, In 7th International Symposium on High Performance Computer Architecture, January, 2001 (see abstract).

Symbiotic Jobscheduling for a Simultaneous Multithreading Processor, Allan Snavely, Dean M. Tullsen, In Ninth International Conference on Architectural Support for Programming Languages and Operating Systems, November, 2000.

Power-Sensitive Multithreaded Architecture, John S. Seng, Dean M. Tullsen, George Z.N. Cai, In International Conference on Computer Design 2000, September, 2000 (see abstract).

Limits of Task-based Parallelism in Irregular Applications, Barbara Kreaseck, Dean M. Tullsen, Brad Calder, In Third International Symposium on High Performance Computing, October, 2000 (see abstract). (a version of this paper also appeared in Interact-4). Best Student Paper award.

Hardware Identification of Cache Conflict Misses, Jamison D. Collins, Dean M. Tullsen, In 32nd Annual International Symposium on Microarchitecture, November, 1999 (see abstract).

ILP Versus TLP on SMT, Nicholas Mitchell, Larry Carter, Jeanne Ferrante, Dean Tullsen, In Supercomputing '99, November 1999.

Classifying Load and Store Instructions for Memory Renaming, Glenn Reinman, Brad Calder, Dean Tullsen, Gary Tyson, Todd Austin, In ACM International Conference on Supercomputing, June 1999.

Storageless Value Prediction Using Prior Register Values, Dean M. Tullsen, John S. Seng, In 26th International Symposium on Computer Architecture, May, 1999.

Selective Value Prediction, Brad Calder, Glenn Reinman, Dean M. Tullsen In 26th International Symposium on Computer Architecture, May, 1999.

Software-Directed Register Deallocation for Simultaneous Multithreaded Processors, Jack L. Lo, Sujay S. Parekh, Susan J. Eggers, Henry M. Levy, and Dean M. Tullsen, IEEE Transactions on Parallel and Distributed Systems, to appear (see abstract).

Instruction Recycling on a Multiple-Path Processor, Steven Wallace, Dean M. Tullsen, Brad Calder, In 5th International Symposium on High Performance Computer Architecture, January, 1999 (see abstract).

Supporting Fine-Grained Synchronization on a Simultaneous Multithreading Processor, Dean M. Tullsen, Jack L. Lo, Susan J. Eggers, Henry M. Levy, In 5th International Symposium on High Performance Computer Architecture, January, 1999 (see abstract, amplified technical report, published version).

Explorations in Symbiosis on Two Multithreaded Architectures, Allan Snavely, Nick Mitchell, Larry Carter, Jeanne Ferrante, Dean Tullsen, In Workshop on Multithreaded Execution, Architecture, and Compilation, January, 1999.

Threaded Multiple Path Execution, Steven Wallace, Brad Calder, Dean M. Tullsen, In 25th Annual International Symposium on Computer Architecture, June, 1998.

Tuning Compiler Optimizations for Simultaneous Multithreading, Jack L. Lo, Susan J. Eggers, Henry M. Levy, Sujay S. Parekh, Dean M. Tullsen, In 30th Annual International Symposium on Microarchitecture (Micro-30), Dec. 1-3, 1997 (see abstract).

Simultaneous Multithreading: A Foundation for Next-generation Processors, Susan J. Eggers, Joel S. Emer, Henry M. Levy, Jack L. Lo, Rebecca L. Stamm, and Dean M. Tullsen, IEEE Micro, September/October 1997, pp. 12-18.

Converting Thread-Level Parallelism Into Instruction-Level Parallelism via Simultaneous Multithreading, Jack L. Lo, Joel S. Emer, Henry M. Levy, Rebecca L. Stamm, Dean M. Tullsen, S. J. Eggers, ACM Transactions on Computer Systems, August 1997, pp. 322-354.

Simultaneous Multithreading, D.M. Tullsen, Ph.D. Thesis, University of Washington, August, 1996.

Exploiting Choice: Instruction Fetch and Issue on an Implementable Simultaneous Multithreading Processor, Dean M. Tullsen, Susan J. Eggers, Joel S. Emer, Henry M. Levy, Jack L. Lo, Rebecca L. Stamm, In 23rd Annual International Symposium on Computer Architecture, May, 1996, REPRINTED IN Readings in Computer Architecture. Winner of 2011 ACM SIGARCH/IEEE-CS TCCA Influential ISCA Paper Award!

Simultaneous multithreading: maximizing on-chip parallelism, Dean M. Tullsen, Susan J. Eggers, Henry M. Levy, In 22nd Annual International Symposium on Computer Architecture, June, 1995. REPRINTED IN 25 Years of the International Symposia on Computer Architecture: Selected Papers, 1998. Winner of 2010 ACM SIGARCH/IEEE-CS TCCA Influential ISCA Paper Award!

Simulation and Modeling of a Simultaneous Multithreading Processor, D.M. Tullsen,In the 22nd Annual Computer Measurement Group Conference, December, 1996

Effective Cache Prefetching on Bus-Based Multiprocessors, Dean M. Tullsen, Susan J. Eggers, ACM Transactions on Computer Systems, pp. 57-88, February, 1995.

Limitations of Cache Prefetching on a Bus-Based Multiprocessor, Dean M. Tullsen, Susan J. Eggers, In 20th Annual International Symposium on Computer Architecture, pp 278-288, May, 1993 (see abstract)

Design and VLSI Implementation of an Online Algorithm, D.M. Tullsen, M.D. Ercegovac, Real Time Signal Processing IX, August, 1988

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If you have comments or suggestions, email me at tullsen at cs.ucsd.edu