cse290arch: Architecture Seminar
Wednesday, 1:00-2:00 (The official schedule says 1:00-2:20. It's wrong.)
The primary objective of the architecture seminar is to keep us abreast
of interesting developments in architecture research with relatively little
Each week everyone reads a paper and one or two students present
it. Presentations are low-key:
Questions? email swanson at cs.ucsd.edu
- Keep it short (aim for 15 minutes) to allow more time for discussion.
- 1-2 slides: a brief summary of the paper.
- 1 slide: strengths.
- 1 slide: weaknesses.
- 1-2 slides: though-provoking questions to get discussion started.
- It's useful if you cut and paste the graphs and important tables onto slides so we can put them up and discuss them as needed.
||The Case for CMP...
||Jack and Laura
||Ganesh and Hung-wei
||Precomputation and backward slices
||Architectural Vulnerability Factors
``A Systematic Methodology to Compute the Architectural Vulnerability
Factors for a High-Performance Microprocessor,'', S. S. Mukherjee,
C. Weaver, J. Emer, S. K. Reinhardt, and T. Austin in MICRO 36:
Proceedings of the 36th annual IEEE/ACM International Symposium on
Microarchitecture, (Washington, DC, USA), p. 29, IEEE Computer Society,
J. Srinivasan, S. V. Adve, P. Bose, and J. A. Rivers, ``The Case for
Lifetime Reliability-Aware Microprocessors,'' SIGARCH Comput. Archit.
News, vol. 32, no. 2, p. 276, 2004.
``The case for a single-chip multiprocessor,'', K. Olukotun, B. A.
Nayfeh, L. Hammond, K. Wilson, and K. Chang in ASPLOS-VII: Proceedings
of the seventh international conference on Architectural support for
programming languages and operating systems, (New York, NY, USA), pp. 2-11,
ACM, 1996, link.
``A case for redundant arrays of inexpensive disks (RAID),'', D. A.
Patterson, G. Gibson, and R. H. Katz in SIGMOD '88: Proceedings of the
1988 ACM SIGMOD international conference on Management of data, (New York,
NY, USA), pp. 109-116, ACM, 1988,
``Retrospective: simultaneous multithreading: maximizing on-chip
parallelism,'', D. M. Tullsen, S. J. Eggers, and H. M. Levy in ISCA
'98: 25 years of the international symposia on Computer architecture
(selected papers), (New York, NY, USA), pp. 115-116, ACM, 1998,
``Simultaneous multithreading: maximizing on-chip parallelism,'',
D. M. Tullsen, S. J. Eggers, and H. M. Levy in ISCA '95: Proceedings of
the 22nd annual international symposium on Computer architecture, (New York,
NY, USA), pp. 392-403, ACM, 1995,
``Transactional Memory: Architectural Support For Lock-Free Data
Structures,'', M. Herlihy and J. E. B. Moss in Proceedings of the
Twentieth Annual International Symposium on Computer Architecture, 1993.
T. Harris and K. Fraser, ``Language support for lightweight
transactions,'' SIGPLAN Not., vol. 38, no. 11, pp. 388-402, 2003.
``Multiscalar processors,'', G. S. Sohi, S. E. Breach, and T. N.
Vijaykumar in ISCA '95: Proceedings of the 22nd annual international
symposium on Computer architecture, (New York, NY, USA), pp. 414-425, ACM,
``Speculative precomputation: long-range prefetching of delinquent
loads,'', J. D. Collins, H. Wang, D. M. Tullsen, C. Hughes, Y.-F. Lee,
D. Lavery, and J. P. Shen in ISCA '01: Proceedings of the 28th annual
international symposium on Computer architecture, (New York, NY, USA),
pp. 14-25, ACM, 2001, link.
``Understanding the backward slices of performance degrading
instructions,'', C. B. Zilles and G. S. Sohi in ISCA '00: Proceedings
of the 27th annual international symposium on Computer architecture, (New
York, NY, USA), pp. 172-181, ACM, 2000,
D. A. Patterson and D. R. Ditzel, ``The case for the reduced
instruction set computer,'' SIGARCH Comput. Archit. News, vol. 8,
no. 6, pp. 25-33, 1980.