NANOELECTRONICS MODELING
Nanoparticle Interconnects
Modeling of interconnects for foldable electronics
Sub 50nm Semiconductor Manufacturing Effects
Impact of Chemical-Mechanical Polishing (CMP) fills
Transistor reliability and aging (hot carrier injection -HCI and bias temperature instability - BTI)
Interconnect reliability (electromigration, stress migration, dielectric breakdown)
Device thermal heating modeling
Double-patterning lithography (DPL) modeling

COMPUTATIONAL MODELING
Statistical Methods
Monte-Carlo alternative methods and PCA-based modeling
Computational Methods
Dr. Topaloglu's research in this area entails speeding up algorithm by use of efficient parallel algorithms and GPU programming

SEMICONDUCTOR CHIP-SCALE ANALYSIS & OPTIMIZATION
Reliability
Full-chip aging analysis
Full-chip interconnect reliability optimization
Performance
Dr. Topaloglu utilizes Design for manufacturability (DFM) and VLSI CAD to solve full-chip problems
Full-chip performance (timing) optimization incorporating IC manufacturing effects such as stress, CMP fills, and aging
Full-chip thermal optimization
Full-chip performance analysis for DPL