BOOKS
R.O. Topaloglu and P. Li, "Recent Topics on Modeling of Semiconductor Processes, Devices and Circuits." To be e-published in 2009.

JOURNALS
Each publication is copyrighted by its publisher. Use this page only for a preview.

Papers with Andrew B. Kahng have author names alphabetically ordered, not by contribution.

[J6] A.B. Kahng, P. Sharma and R.O. Topaloglu, "Chip optimization through STI stress-aware placement perturbations and fill insertion." IEEE Trans. on Computer-Aided Design, 27(7), 2008. (.pdf)

[J5] A.B. Kahng and R.O. Topaloglu, "DOE-based extraction of CMP, active and via fill impact on capacitances." IEEE Trans. on Semiconductor Manufacturing, 21(1), 2008, pp. 22-32. (.pdf)

[J4] R.O. Topaloglu, "Process variation-aware multiple-fault diagnosis of thermometer-coded current-steering DACs." IEEE Trans. on Circuits and Systems-II: Analog and Digital Signal Processing, 54(2), 2007, pp. 191-195. (.pdf)

[J3] E.S. Erdogan, R.O. Topaloglu, O. Cicekoglu, H. Kuntman and A. Morgul, "Novel multiple function analog filter structures and a dual-mode multifunction filter." International Journal of Electronics, 93(9), 2006, pp.637-650, DOI: 10.1080/00207210600711713. Listed as #5 in 2006 most downloaded articles.

[J2] E.S. Erdogan, R.O. Topaloglu, O. Cicekoglu and H. Kuntman, "New current-mode special function continuous time active filters employing only OTAs and OPAMPs." International Journal of Electronics, 91(6), 2004, pp. 345-359.

[J1] R.O. Topaloglu, H. Kuntman and O. Cicekoglu, "Current-input current-output notch and bandpass analog filter structures as alternatives to active-R circuits, Frequenz", 57(5-6), 2003, pp. 123-127.

CONFERENCES
[C21] K. Jeong, A. B. Kahng and R. O. Topaloglu, "Is Overlay Error More Important Than Interconnect Variations in Double Patterning?" Proc. ACM International Workshop on System-Level Interconnect Prediction, 2009.

[C20] A. Sultan, J. Faricelli, S. Suryagandh, H. VanMeer, K. Mathur, J. Pattison, S. Hannon, G. Constant, K. Kumar, K. Carrejo, J. Meier, R. Topaloglu, D. Chan, U. Hahn and T. Knopp, CAD utilities to comprehend layout-dependent stress effects in 45 nm high-performance SOI custom macro design, Proc. IEEE International Symposium on Quality Electronic Design, 2009.

[C19] R.O. Topaloglu, "Interconnect variability analysis for double patterning lithography." Invited Paper, VLSI Multilevel Interconnection Conference, 2008.

[C18] A.B. Kahng, K. Samadi and R.O. Topaloglu, "Recent topics in CMP-related IC Design for Manufacturing," Proc. Advanced Metallization Conference, Invited Paper, 2008.

[C17] R.O. Topaloglu, "Process variation characterization and modeling of nanoparticle interconnects for foldable electronics," Proc. IEEE International Symposium on Quality Electronic Design, 2008. (.pdf)

[C16] R.O. Topaloglu, "Via chamfering modeling for improved MIM capacitance silicon correlation." Proc. International VLSI/ULSI Multilevel Interconnection Conference (VMIC), 2007.

[C15] A.B. Kahng and R.O. Topaloglu, "Performance-aware CMP fill pattern optimization." Invited Paper, Proc. International VLSI/ULSI Multilevel Interconnection Conference (VMIC), 2007.

[C14] A.B. Kahng, P. Sharma and R.O. Topaloglu, "Exploiting STI stress for performance." Proc. IEEE/ACM International Conference on Computer-Aided Design, 2007, pp. 83-90. (.pdf)

[C13] R.O. Topaloglu, "Standard cell and custom circuit optimization using dummy diffusions through STI width stress effect utilization." Proc. IEEE Custom Integrated Circuits Conference, 2007, pp. 619-622. (.pdf)

[C12] A.B. Kahng and R.O. Topaloglu, "A DOE set for normalization-based extraction of fill impact on capacitances." Best Paper Award, Proc. IEEE International Symposium on Quality Electronic Design, 2007, pp. 467-474. (.pdf)

[C11] R.O. Topaloglu, "Energy-minimization model for fill synthesis." Proc. IEEE International Symposium on Quality Electronic Design, 2007, pp. 444-451. (.pdf)

[C10] A.B. Kahng and R.O. Topaloglu, "A TCAD-based study of fill pattern and via fill impact on low-k dielectric stress." Invited Paper, Proc. International Chemical-Mechanical Planarization for ULSI Multilevel Interconnection Conference (CMP-MIC), 2007, pp. 337-346.

[C9] A. B. Kahng and R. O. Topaloglu, "Interconnect matching design rule inferring and optimization through correlation extraction." Proc. IEEE International Conference on Computer Design, 2006, pp. 222-229. (.pdf)

[C8] R.O. Topaloglu, "Monte Carlo-alternative probabilistic simulations for analog systems," Proc. IEEE International Symposium on Quality Electronic Design, 2006, pp. 249-253. (.pdf)

[C7] A.B. Kahng and R.O. Topaloglu, "Generation of design guarantees for interconnect matching", Proc. IEEE/ACM System Level Interconnect Prediction Workshop, 2006, pp. 29-34. (.pdf)

[C6] R.O. Topaloglu, "Early, accurate and fast yield estimation through Monte Carlo-alternative probabilistic behavioral analog system simulations," Proc. IEEE VLSI Test Symposium, 2006, pp. 136-142. (.pdf)

[C5] V. Wason, J.X. An, J.-S. Goo, Z.-Y. Wu, Q. Chen, C. Thuruthiyil, R. Topaloglu, P. Chiney, and A. Icel, "Statistical compact modeling and Si verification methodology." Invited Paper, Proc. International Conference on Solid-State and Integrated-Circuit Technology (ICSICT), 2006, pp. 1198-1201.

[C4] R.O. Topaloglu and A. Orailoglu, "Forward discrete probability propagation method for device performance characterization under process variations." Proc. Asia and South Pacific Design Automation Conference, 2005, pp. 220-223. (.pdf)

[C3] R.O. Topaloglu and A. Orailoglu, "A DFT approach for diagnosis and process variation-aware structural test of thermometer coded current steering DACs." Proc. IEEE/ACM/EDAC Design Automation Conference, 2005, pp. 851-856. (.pdf)

[C2] R.O. Topaloglu, A. Orailoglu, "On mismatch in the deep sub-micron era - from physics to circuits." Proc. Asia and South Pacific Design Automation Conference, 2004, pp. 62-67. (.pdf)

[C1] R.O. Topaloglu, H. Kuntman and O. Cicekoglu, "Novel notch and bandpass filter structures using OTAs and OPAMPs." Proc. International Conference on Electrical and Electronics Engineering, 2001, pp. 63-67.