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Mulong LUO

Graduate Student
University of California, San Diego

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I am a graduate student at Computer Science and Engineering Department, University of California, San Diego. I received my B.S. degree (highest honors) in Microelectronics from Peking University during 2010-2014. Recently, I found my research interests in cyber-physical systems (CPS), architecture and applications. Previously, I have also accomplished works in electronic design automation, semiconductor device modeling, and data mining.

muluo AT cs.ucsd.edu

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Mulong Luo

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Mulong Luo

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Vita

Education

  • University of California, San Diego                                    
    2014-Present

    Pursuing a graduate degree in the Department of Computer Science and Engineering

  • Peking University                                    
    2010-2014

    Received B.S. degree with highest distinctions in Microelectronics from the school of Electronic Engineering and Computer Science.

  • No. 1 Middle School attached to Central China Normal University
    2007-2010

    Received high school diploma.

Research Experience

  • A Framework for Realtime Mobile Computation Offloading
    2016 UCSD

    Designed and implemented a client-server framework for realtime mobile computation offloading. Developed scheduling policy to avoid conflict and reduce the response time of the server. Defined and Implemented application programming interface for developer. Implemented time synchronization between client and server. Deployed the system on Raspberry Pis and demostrated QoS improvements for facial detection and simultaneous localization and mapping.

  • Benchmark of An Implementation of Lightweight Real-Time Framework in Go Programming Language
    2016 UCSD

    Instrumented Go Language compiler to support real-time applications. Design schedulability test to benchmark the RealTime Go with different scheduling policies.

  • Integer Programming-based DRAM Design Automation
    2014-2015 UCSD

    Built a fast signal-criticality and timing window aware timer for DRAM interconnect design automation. Proposed and Implemented mixed-integer linear programming and pair-swapping optimization techiques to minimize the delay uncertainties of signals. Verified the optimization results with testcases provided by industry partners, achieving 24% delay uncertainty reduction.

  • Machine Learning-based VLSI Timing Prediction
    2015 UCSD

    Implemented signal integrity, temperature and voltage drop-aware timing analysis flow using industry standard tools. Built machine-learning models to predict SI timing without running expensive and time-consuming SI tools, achieving worst-case eror of 6.9% for path delay prediction. Created artificial testcases taking SI, temperature and voltage drop to accelerate model training.

  • Monte Carlo-based CMOS Circuit/Device Simulation  
    2012-2014 Peking University

    Developed the Monte Carlo-based framework for SPICE simulation of trap induced degration, e.g. Random Trap flucation, Bias Temperature Instability and Random Telegraph Noise. Proposed and verified a new model for the statistics of AC RTN, well explained the experimental observations. Evaluated the SI of CMOS combinational circuits and failure probability of SRAM cell with trap-induced effects using our framwork embedded in EDA tools.

Industry Experience

  • Synopsys Inc., Mountain View, CA
    2016

    Implemented new track assignment congestion map models in the industry-leading VLSI layout design automation tools. Improved the qualtifty of results.

  • Selected Publications

    • Cyber-Physical Systems

      Z. Fang, M. Luo, H. Zhuang, and R. Gupta, "Go-RealTime: A Lightweight Framework for Multiprocessor Real-Time System in User Space, " in Proceeding of 4th IEEE International Workshop on Real-Time Computing and Distributed Systems in Emerging Applications, 2016.

      Data Mining

      A. B. Kahng, M. Luo, G.-J. Nam, S. Nath, D. Z. Pan, G. Robins,"Towards Metrics of Design Automation Research Impact," in Proceedings of ACM/IEEE International Conference on Computer-Aided Design (ICCAD), 2015, pp. 263-270.

      Electronic Design Automation

      A. B. Kahng, M. Luo, S. Nath,"SI for Free: Machine Learning of Interconnect Coupling Delay and Transition Effects," in Proceedings of ACM/IEEE System Level Interconnect Prediction Workshop(SLIP), 2015.

      S. Bang, K. Han, A. B. Kahng, M. Luo,"Delay Uncertianty and Signal Criticality Driven Routing Channel Optimization for Advanced DRAM Products," in Proceedings of ACM/IEEE Asia and South Pacific Design Automation Conference (ASP-DAC), 2016, to appear.

      Semiconductor Device Modeling

      D. Mao, S. Guo, R. Wang, M. Luo, R. Huang, "Deep Understanding of Random Telegraph Noise (RTN) effects on SRAM Stability, " in Proceeding of International Symposium on VLSI Technology, Systems and Application, 2016 (Best Student Paper Candidate).

      M. Luo,  R. Wang, S. Guo, J. Wang, J. Zou, and R. Huang, "Impacts of Random Telegraph Noise (RTN) on Digital Circuits, "IEEE Transactions on Electron Devices (T-ED) 62(6) 2015, pp. 1725-1732.

      M. Luo, et al.,"Compact Modeling of Random Telegraph Noise in Nanoscale MOSFETs and Impacts on Digital Circuits," in Technical Digest of International Symposium on VLSI Technology, Systems and Applications, 2014, pp.1-2.

      R. Wang*, M. Luo, et al., "A Unified Approach for Trap-Aware Device/Circuit Co-Design in Nanoscale CMOS Technology," in Proceedings of IEEE International Electron Devices Meeting (IEDM), 2013, pp. 834-837. *-Mulong Luo (1st student author)'s research advisor during this work

       

Implementation and Benchmark of Go-RealTime

Instrumented Go Language compiler to support real-time applications. Design schedulability test to benchmark the RealTime Go with different scheduling policies. REACTION 2016 cyber-physical systems

NoQueue: A Real-Time Mobile Offloading Framework

Designed and implemented a client-server framework for realtime mobile computation offloading. Developed scheduling policy to avoid conflict and reduce the response time of the server. Defined and Implemented application programming interface for developer. Implemented time synchronization between client and server. Deployed the system on Raspberry Pis and demostrated QoS improvements for facial detection and simultaneous localization and mapping. In Progress cyber-physical systems

Data Mining of Digital Libraries for Measuring Research Impact

Use text mining (latent Dirichlet allocation) to analysis 47000+ conference and journal papers of design automation from 1964-2014 and inter-patent citation graph over 759000+ DA-related patents. Characterized the time evolution of research topic over the years. Discovered the inner connection between the academic research literature and industry production. ICCAD 2015 data mining

Machine Learning-based VLSI Timing Prediction

Implemented signal integrity, temperature and voltage drop-aware timing analysis flow using industry standard tools. Built machine-learning models to predict SI timing without running expensive and time-consuming SI tools, achieving worst-case eror of 6.9% for path delay prediction. Created artificial testcases taking SI, temperature and voltage drop to accelerate model training. SLIP 2015 EDA machine learning

Integer Programming-based DRAM Design Automation

Built a fast signal-criticality and timing window aware timer for DRAM interconnect design automation. Proposed and Implemented mixed-integer linear programming and pair-swapping optimization techiques to minimize the delay uncertainties of signals. Verified the optimization results with testcases provided by industry partners, achieving 24% delay uncertainty reduction. ASP-DAC 2016 EDA

Monte Carlo-based CMOS Circuit/Device Simulation

Developed the Monte Carlo-based framework for SPICE simulation of trap induced degration, e.g. Random Trap flucation, Bias Temperature Instability and Random Telegraph Noise. Proposed and verified a new model for the statistics of AC RTN, well explained the experimental observations. Evaluated the SI of CMOS combinational circuits and failure probability of SRAM cell with trap-induced effects using our framwork embedded in EDA tools. TED 2015 IEDM 2013 VLSI-TSA 2014 device modeling

  • Cyber-Physical Systems

    [GoRealTime] Z. Fang, M. Luo, H. Zhuang, and R. Gupta, "Go-RealTime: A Lightweight Framework for Multiprocessor Real-Time System in User Space, " in Proceeding of 4th IEEE International Workshop on Real-Time Computing and Distributed Systems in Emerging Applications, 2016.

    Data mining

    [DAMetric] A. B. Kahng, M. Luo, G.-J. Nam, S. Nath, D. Z. Pan, G. Robins,"Towards Metrics of Design Automation Research Impact," in Proceedings of ACM/IEEE International Conference on Computer-Aided Design (ICCAD), 2015, pp. 263-270. [pdf]

    Electronic Design Automation

    [gt1gt2] A. B. Kahng, M. Luo, S. Nath,"SI for Free: Machine Learning of Interconnect Coupling Delay and Transition Effects," in Proceedings of ACM/IEEE System Level Interconnect Prediction Workshop(SLIP), 2015. [pdf]

    [SamInterconnect] S. Bang, K. Han, A. B. Kahng, M. Luo,"Delay Uncertianty and Signal Criticality Driven Routing Channel Optimization for Advanced DRAM Products," in Proceedings of ACM/IEEE Asia and South Pacific Design Automation Conference (ASP-DAC), 2016.

    Semiconductor Device Modeling

    [RTNCircuit] M. Luo,  R. Wang, S. Guo, J. Wang, J. Zou, and R. Huang, "Impacts of Random Telegraph Noise (RTN) on Digital Circuits, "IEEE Transactions on Electron Devices (T-ED) 62(6) 2015, pp. 1725-1732. [pdf]

    [RTNCh] J. Zou, R. Wang, M. Luo, et al., "Deep understanding of AC RTN in MuGFETs through New Characterization Method and Impacts on Logic Circuits," in Proceedings of IEEE Syposium on VLSI Technology (VLSI), 2013, pp.186-187. [pdf]

    [UniTrap] R. Wang*, M. Luo, et al., "A Unified Approach for Trap-Aware Device/Circuit Co-Design in Nanoscale CMOS Technology," in Proceedings of IEEE International Electron Devices Meeting (IEDM), 2013, pp. 834-837. *-Mulong Luo (1st student author)'s research advisor during this work. [pdf]

    [CompRTN]M. Luo, et al.,"Compact Modeling of Random Telegraph Noise in Nanoscale MOSFETs and Impacts on Digital Circuits," in Technical Digest of International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA), 2014, pp.1-2. [pdf]

    [TrapCha] S. Guo, P. Ren, R. Wang, Z. Yu, M. Luo, et al., "A New Efficient Method for Characterizing Time Constants of Switching Oxide Traps in Full Swing Window," in Proceedings of IEEE International Reliability Physics Symposium(IRPS), 2014, pp.XT.14.1 - XT.14.4. [pdf]

    [DTCha] S. Guo, R. Huang, P. Hao, M. Luo, et al.,"DTMOS Mode as an Effective Solution of RTN Suppresion for Robust Device/Circuit Co-Design," in Proceedings of IEEE International Electron Devices Meeting (IEDM), 2014. pp. 319-322. [pdf]

    [CompNoise] J. Zou, R. Wang, S. Guo, M. Luo, et al.,"New Understanding of State-Loss in Complex RTN: Statistical Experimental Study, Trap Interaction Models, and Impact on Circuits," in Proceedings of IEEE International Electron Devices Meeting (IEDM), 2014. pp. 832-835. [pdf]

    [BTI-SRAM] D. Mao, S. Guo, R. Wang, M. Luo, R. Huang, "Deep Understanding of Random Telegraph Noise (RTN) effects on SRAM Stability, " in Proceeding of International Symposium on VLSI Technology, Systems and Application, 2016 (Best Student Paper Candidate).

     

My Address

EBU3B Room 2142

University of California, San Diego

9500 Gilman Drive

La Jolla, CA 92093-0404, USA

Phone Number

(+1)858-263-6752

Email

muluo AT cs DOT ucsd DOT edu