CSE.291 Design of Parallel VLSI Architectures - Fall 2007

    

Course Goals

This class is designed to enable students to be able to execute aggressive projects involving both VLSI and parallel computer architecture. Course readings will be drawn from the literature, and will focus on the implications of modern VLSI design on parallel architectures (such as multicore, or tiled microprocessors or stream processors.)

Course Project

A substantial portion of the class will be in a self-directed team project in which students will propose an architectural structure and perform an implementation study using VLSI CAD tools.

Example projects include NUCA (non-uniform cache architecture), interconnection networks, scalar operand networks, shared memory protocol engines, FPGA fabrics, heterogeneous multicore elements, distributed superscalar wakeup logic, transactional memory, or memory dependence speculation hardware. Alternatively, students may propose a project of their own choosing, possibly motivated by their own research. Students with CAD/VLSI experience may find it useful to team up with students with architecture experience and visa versa. 		      
[Michael Taylor]
Prof. Michael Taylor

Schedule

DateMaterialDue & Discussed todayNotes
Th9/27Class Overview/Raw
The Raw Microprocessor: A Computational Fabric for Software Circuits and General Purpose Programs,
by Michael Bedford Taylor, Jason Kim, Jason Miller, David Wentzlaff, Fae Ghodrat, Ben Greenwald, Henry Hoffman, Jae-Wook Lee, Paul Johnson, Walter Lee, Albert Ma, Arvind Saraf, Mark Seneski, Nathan Shnidman, Volker Strumpen, Matt Frank, Saman Amarasinghe and Anant Agarwal.
IEEE Micro, March/April 2002. (pdf)

The Raw Implementation, from Tiled Microprocessors, Chapter 4, Michael Taylor, Feb 2007. (pdf)
Tu10/2Lab 1 Overview
First Part of Lab One out.
Th10/4Technology

Impact of Technology on Architecture, John H. Edmondson. From Design of High Performance Microprocessor Circuits, eds. Anantha Chandrakasan et al.
Tu10/9Lab 1 DiscussionFirst Part of Lab 1

Th10/11Out-of-Order Arch and Circuits
The Alpha 21264 Microprocessor, R. E. Kessler, IEEE Micro 1999.

Issue Logic for a 600-MHz Out-of-Order Execution Microprocessor, Farrell and Fischer, IEEE Journal of Solid-state Circuits, Vol 33 No. 5 May 1998.
Tu10/16Lab 1 DiscussionSecond Part of Lab 1

Th10/18Reading

Tu10/23Project ProposalsProject Proposal & Presentation

Th10/25Reading

Tu10/30Project StatusProject Status 1 Slides & Presentation

Th11/1Reading

Tu11/6Project StatusProject Status 2 Slides & Presentation

Th11/8Reading

Tu11/13Project StatusProject Status 3 Slides & Presentation

Th11/15Reading

Tu11/20Project StatusProject Status 4 Slides & Presentation

Th11/22Reading

Tu11/27Project StatusProject Status 5 Slides & Presentation

Th11/29Reading

Tu12/4Project FinalProject Final Writeup & Presentations


A multi-core processor

Announcements

September 26, 2007None yet.

Materials

  • IEEE Explore (free access from UCSD network) For IEEE publications.
  • ACM Portal (free access from UCSD network) For ACM publications.

    Grading

    Approximate grading percentages (subject to change with advance notice):

    Class Participation: 25 %
    Paper Expert 15 %
    Lab(s): 10 %
    Project: 50 %


    Since the class is small, class participation is essential and will contribute significantly to the grade (25%). In addition, you will be the leader of the discussion of a paper in the class (15%). For this, you are expected to prepare slides that overview the content of the assigned paper for the class and provide potential supplementary material for items which raised questions in the paper. The first lab is intended to get you acquainted with the usage of the Synopsys CAD tool flow (as well as datapath and control-based design) for the purposes of your project (10%). Finally, the project will contribute to the largest portion of your grade (50%) and time spent in the class.

    Prerequisites

    Either 240A/240B (graduate architecture) or 241A (graduate VLSI/CAD) or equivalent, or CAD tool experience, or permission of instructor.

    Meeting Times

    Meeting times: Tu/Th 11 am-12:20 am CSE Building (ebu 3b) RM 4217
    Office hours: By appointment CSE Building (ebu 3b) RM 4110