Michael B. Taylor
UCSD Center for Dark Silicon
Computer Science and Engineering
University of California, San Diego 92093
EBU 3b 3202
+1 use email
+1 (858) 534 7029
I have been a professor in the Department of Computer Science and
Engineering at the University of California, San Diego since 2005. I
received a PhD in Electrical Engineering and Computer Science from MIT. I
was lead architect of the 16-core MIT Raw tiled
multicore processor, one of the earliest multicore processors, which was commercialized into the Tilera
TILE64 architecture. I co-authored the earliest published research on dark silicon,
including a paper that derives the utilization wall that causes dark silicon.
I occasionally help companies and other legal professionals evaluate their patent portfolios,
and provide advice to companies leveraging the Tilera TILE64 architecture. I have broad expertise in hardware and software, and on the Bitcoin cryptocurrency.
My research is funded primarily by the National Science Foundation (NSF), including the Secure and Trustworthy Cyberspace Program, and DARPA/MARCO's C-FAR.
Between the gaps at school, I worked on Apple's NuKernel microkernel, and co-wrote the first version
of Connectix Virtual PC, an x86-to-PowerPC dynamic translation engine, which was acquired by Microsoft. I also
contributed to the ChipWrights Visual Signal Processor in its
I received the NSF CAREER Award in 2009 and tenure in 2012.
My research sponsors:
I direct the
UCSD Center for Dark Silicon.
My colleagues and I were among the first to demonstrate
the existence of a utilization wall
which says that with the progression of Moore's Law, the percentage of a chip that we can actively use within a chip's power budget is dropping exponentially! The remaining silicon
that must be left unpowered is now referred to as Dark Silicon.
Our research on Conservation Cores and GreenDroid proposes new architectures that exploit dark silicon. Our paper on the The Four Horsemen (slides) overviews the landscape of architectural approaches to addressing dark silicon.
In addition to researching architectures for dark silicon, I look more broadly at sources of under-utilization
in current day chips, spanning from
a) power limitations because of poor CMOS scaling, b) overly large software engineering costs for parallelizing programs for multicore chips, and
c) lack of parallel application domains.
My research attacks each of these problems by 1) reinventing processor design to make use of dark silicon, 2) utilizing existing cores better through better parallel software engineering tools and 3) finding new parallel application classes to put cores to work:
The GreenDroid Mobile Applications Processor, which employs
Conservation Cores to fight dark silicon.
Our ASPLOS 2010 paper is one of the earliest
peer-reviewed architecture papers to have a cogent description of the utilization wall that
causes the Dark Silicon problem, and to propose specialization as an architectural solution.
||Our Hotchips 2010 work
GreenDroid: A Mobile Application Processor for a Future of Dark Silicon flushes out this proposal,
and is quite possibly the first published academic use of the term Dark Silicon. This was
followed up with
this March 2011 IEEE Micro paper. (Here is the Hotchips talk on youtube.) |
||Our work, Is Dark Silicon Useful? Harnessing the Four Horsemen of the Coming Dark Silicon Apocalypse, which appeared in DAC and DaSi 2012, and is followed by a paper in IEEE Micro 2013, is the first paper to overview the landscape of architectural approaches that try to address the dark silicon problem. We describe the four horsemen -- four approaches to dealing with dark silicon, each with deep-seated challenges but also unique capabilities. See the slides for a very entertaining presentation on the shrinking, dim, specialized, and deux ex machina horsemen.|
|| Kremlin, a tool that, given a serial program,
tells you which regions to parallelize.
To create Kremlin, we developed a novel dynamic analysis, hierarchical critical path analysis, to detect parallelism across nested regions of the program,
which connects to a parallelism planner which evaluates many potential parallelization to figure out the best way for the user to parallelize the target program.
|| the San Diego Vision Benchmark Suite, which distills the emerging computer vision application class into a collection
of nine benchmarks written in a research-friendly style. This work was advised by Prof. Serge Belongie, a member of UC San Diego's top-notch vision faculty.
- Bitcoin and The Age of Bespoke Silicon
(Read this for a stirring account of the Bitcoin mining community that
heralds a new age of
hardware innovation tailored to emerging application domains)
Michael Bedford Taylor
International Conference on Compilers, Architecture and Synthesis for Embedded Systems (CASES), Sept 2013. (Talk) (Paper) (bib)
- Is Dark Silicon Useful?
Harnessing the Four Horsemen of the Coming Dark Silicon Apocalypse
(Cite this for first synthesis of approaches to attacking Dark Silicon.)
Michael B. Taylor
Design Automation Conference (DAC), June 2012. (pdf) (bib) (slides).
Also presented at the Dark Silicon Workshop (DaSi) 2012.
- Conservation Cores: Reducing the Energy of Mature Computations.
(Cite this for first peer-reviewed Utilization Wall & Dark Silicon Analysis.
Also for heterogeneity as a solution to dark silicon problem.)
Ganesh Venkatesh, John Sampson, Nathan Goulding, Saturnino Garcia, Slavik Bryskin, Jose Lugo-Martinez, Steven Swanson, and Michael Bedford Taylor.
Architectural Support for Programming Languages and Operating Systems (ASPLOS), March 2010. (pdf) (talk pdf, talk ppt) (bib)
- GreenDroid: A Mobile Application Processor for a Future of Dark Silicon
(Cite this for dark silicon's impact on multicore scaling.
Also, for the GreenDroid massively heterogeneous processor.)
Nathan Goulding, Jack Sampson, Ganesh Venkatesh, Saturnino Garcia, Joe Auricchio, Jonathan Babb, Michael Bedford Taylor and Steven Swanson.
Proceedings of HOTCHIPS, August 2010. (pdf) (talk ppt) (bib) (youtube)
- The GreenDroid Mobile Application Processor: An Architecture for Silicon's Dark Future
Nathan Goulding-Hotta, Jack Sampson, Ganesh Venkatesh, Saturnino Garcia, Joe Auricchio, Po-Chao Huang, Manish Arora, Siddhartha Nath, Jonathan Babb,
Steven Swanson, and Michael Bedford Taylor.
IEEE Micro, March 2011. (pdf) (bib)
- Kremlin: Rebooting and Rethinking gprof for the Multicore Age (Cite this for Kremlin.)
(aka Automatic Parallelism Planning and Discovery with Kremlin)
Saturnino Garcia, Donghwan Jeon, Chris Louie, and Michael Bedford Taylor.
Programming Language Design and Implementation (PLDI), June 2011. (pdf) (bib)
- SD-VBS: The San Diego Vision Benchmark Suite.
Sravanthi Kota Venkata, Ikkjin Ahn, Donghwan Jeon, Anshuman Gupta, Christopher Louie, Saturnino Garcia, Serge Belongie, and Michael Bedford Taylor.
IEEE International Symposium on Workload Characterization (IISWC), October 2009. (pdf) (Download SD-VBS) (bib)
- Evaluation of the Raw Microprocessor:
An Exposed-Wire-Delay Architecture for ILP and Streams
by Michael B Taylor, Walter Lee, Jason Miller, David Wentzlaff, Ian Bratt, Ben Greenwald, Henry Hoffmann, Paul Johnson, Jason Kim, James Psota, Arvind Saraf, Nathan Shnidman, Volker Strumpen, Matt Frank, Saman Amarasinghe, and Anant Agarwal.
Proceedings of the International Symposium on Computer Architecture (ISCA), June 2004. (pdf) (bib)
- The Raw Microprocessor:
A Computational Fabric for Software Circuits and General Purpose Programs,
by Michael B Taylor, Jason Kim, Jason Miller, David Wentzlaff, Fae Ghodrat, Ben Greenwald, Henry Hoffman, Jae-Wook
Lee, Paul Johnson, Walter Lee, Albert Ma, Arvind Saraf, Mark Seneski, Nathan Shnidman, Volker Strumpen, Matt Frank, Saman Amarasinghe and Anant Agarwal.
IEEE Micro, March/April 2002. (pdf) (bib)
- Scalar Operand Networks,
by Michael B Taylor, Walter Lee, Saman Amarasinghe, and Anant Agarwal.
IEEE Transactions on Parallel and Distributed Systems (Special Issue on On-chip Networks) (TPDS), February 2005.
(Appendix pdf) (bib)
|Oct 2013|| Because of some of my Bitcoin knowledge, a few newspapers, radio shows, and a TV show interviewed me about Bitcoin, Tor and the Silk Road takedown:
|Sep 2013|| I helped a reporter from the Wall Street Journal put together this front page article on Bitcoin mining.
|Sep 2013 || New CASES paper, Bitcoin and the Age of Bespoke Silicon.
|Sep 2013 || New IEEE Micro paper, A Landscape of the New Dark Silicon Design Regime.
|May 2013|| |
|My PhD student, Jack Sampson || -> tenure-track assistant professor @ Penn State.
|My PhD student, Saturnino Garcia || -> tenure-track assistant professor @ University of San Diego. |
|June 2012||I presented my paper
Is Dark Silicon Useful?|
Harnessing the Four Horsemen of the Coming Dark Silicon Apocalypse (slides) at DAC 2012 and DaSi 2012.
|November 2012||Quoted in this article in the November 2012 IEEE Computer Magazine on Exascale computing.
|May 2012||Quoted right at the beginning of this May 2012 IEEE Computer Magazine Article on Dark Silicon, right after Bill Dally! GreenDroid and Conservation Cores get a big shout-out for being a key approach for attacking the Dark Silicon problem.
|March 2011|| GreenDroid IEEE Micro article, The GreenDroid Mobile Application Processor: An Architecture for Silicon's Dark Future now available!
|Nov 2010|| UCSD ACM Programming Team, which I coach, invited to Worlds in Egypt!
|Aug 2010|| We present our GreenDroid mobile application processor design at Hotchips! Our Hotchips work was the only academic talk in the entire conference.|
Broad coverage in the media:
|May 2010|| HOTCHIPS paper on our C-core-based chip accepted: |
GreenDroid: A Mobile Application Processor for a Future of Dark Silicon.
First conference publication to have dark silicon in the title.
Nov 2009|| Just released The San Diego Vision Benchmark Suite, a benchmark for the vision application domain, written in MATLAB and clean C.
It's available at parallel.ucsd.edu/vision.
|Nov 2009|| Our paper, Conservation Cores: Reducing the Energy of Mature Computations, was accepted into ASPLOS.|
If you read one architecture paper this year, read this ASPLOS Paper. First paper that describes the utilization wall that is the
source of dark silicon, and proposes that heterogeneity is the answer.
|July 2009|| Successfully passed the FAA written test and landed an airplane four times at Long Beach Airport (LGB)!
|June 2009|| National Science Foundation CAREER Award: Energy-Efficient Parallel Architectures for Computer Vision.
Who came up with the term "dark silicon"?
The first use of the term in print was a quote by Bob Metcalfe in March 1997 in the IEEE Internet Computing magazine. However
he was referring to all of the sand in the world that has not yet been turned into chips!
The first mention of the term I've seen in its current context was by ARM CTO Mike Muller at ARM techcon in October 2009. I've heard other folks
say that the term was used by others in ARM and/or HiPeaC community earlier than then. Although ARM techcon happened
after we had submitted our ASPLOS paper in Aug 2009 that discussed the utilization wall,
we thought it was genius and decided to use the term in the title of our immediately following
Hotchips 2010 paper.
How did our group arrive at the utilization wall which causes Dark Silicon, and specialization as an approach to attacking it?
In 2003, I spent a few months reading 300+ ISSCC
and IEDM papers with the goal of comparing the (very different) IBM CMOS7SF
and Intel P858 fabrication processes as part of a Raw-versus-Pentium-3 section of the Raw ISCA paper I was working on.
I was also trying to understand VLSI scaling better so that we could make better proofs about Raw's optimality.
In 2004, I was trying to come up with some ideas for research as a faculty member.
I decided to analyze the scalability of multicore chips like Raw across process generations. Using skills picked up from the study
I did for the Raw ISCA paper,
I arrived at the conclusion that there was an exponentially worsening power issue with multicore scaling and that the problem
was the utilization wall and the dark silicon it creates. The analysis is the same as appears in our subsequent grant proposals and papers.
On the interview trail for faculty positions in 2005, I tried to sell the idea of the utilization wall
one-on-one with interviewing faculty and further proposed that the "ugly chip" (a massively heterogeneous design) was
a logical response. Most everybody didn't believe me or thought it was a terrible idea (James Hoe of CMU, to his credit,
thought it was interesting.).
In 2006, as brand new faculty members,
Steve Swanson and I cowrote a peer-reviewed 2006 NSF proposal that
outlined the utilization wall and created a plan for exploring massively heterogeneous solutions.
(Indeed, Steve named our analysis the
utilization wall, and already himself had a CAREER award on software aspects of heterogeneity.)
(Here is a April 2007 snapshot of our public website talking about the utilization wall.)
After one round
of rejection by peer review, the proposal was funded. The utilization wall
appears in the abstract of our NSF Award in July 2008.
many paper resubmissions, countless co-advising trials and tribulations, we
finally got the utilization wall in peer-reviewed academic literature in this March 2010 ASPLOS paper.
MIT Raw Processor
As one of the lead students in the
MIT Raw project, I led the design and implementation
of the Raw microprocessor, which targeted the leading VLSI technology of the time.
I also contributed heavily to almost all of the software systems that we built to support the
Raw was one of the earliest fabricated multicore processors, with 16 cores on a single die, back in 2002.
The purpose of Raw was to demonstrate architectural solutions to scalability problems
in modern day microprocessors. The Raw architecture exposes the transistor resources
of VLSI chips through the tile abstraction, the pin resources through the
I/O port abstraction, and the wiring resources
through on-chip networks. Raw was commercialized into the Tilera TILE64 architecture.
Because the Raw architecture exposed the on-chip resources more effectively than existing
sequential architectures (for instance the P6 micro-architecture, the basis of
the Pentium-M), Raw was able to outperform Intel desktop
processors, implemented with better process technology, across a variety of applications.
One of the key ideas that came out of the Raw research was the
formulation of the Scalar
Operand Network (SON), a unique class of sub-nanosecond network
responsible for routing operands between functional units and memories
in a distributed microprocessor.
My team implemented the 16-tile Raw microprocessor, shown to
the upper-left, in IBM's SA-27E 180 nm 6-layer Cu ASIC process. The
18.2 mm x 18.2 mm chip was, at least at the time, the largest design
that the IBM ASIC division had targeted for SA-27E. Each tile contains
computing power equivalent to a single-issue pipelined processor. We
taped out the chip in August '02, and received prototypes back in late
October '02. The motherboard was assembled January '03. A
supercomputer prototype, based on 4-chip boards, that scaled to 64 Raw chips (1024-issue) was
More pictures are available here.
Technology Policy Advocacy
Here are my notes about Getting Interviewed as an Expert on TV, based on my experiences getting interviewed by various newspapers, radio shows, and a live TV news program about Bitcoin and the Silk Road.
Testimony regarding Massachusetts House Bill No. 2743, entitled An Act to Improve Broadband and Internet Security,
Massachusetts Joint Committee On Criminal Justice on April 2, 2003.
This testimony was referenced by Ed Felton's Freedom to Tinker website and discussed
in a law journal article:
"Super-DMCA" Statutes: Putting Hollywood in Charge of Internet Business,
Matthew A. Verga, Wake Forest Intellectual Property Law Journal 104, May 2004.
Prof. Michael B. Taylor|
Center for Computer Science and Engineering
University of California, San Diego
9500 Gilman Drive EBU 3b-3202 MC 0404
La Jolla, CA 92093-0404