1. Improved IC Design Floorplan Generation using Ceiling and Floor Contours on an O-Tree Structure, C.K. Cheng and Pei-Ning Guo, US Patent 6,282,694, 8/28/2001.
2. Interconnect Delay Driven Placement and Routing of an Integrated Circuit Design, C.K. Cheng and So-Zen Yao, US Patent 6,327,693, 12/4/2001.
3. Method and Apparatus for Clock Tree Solutions Synthesis based on Design Constraints, C.K. Cheng and Jiang-Jih Chao, US Patent 6,367,060, 4/2/2002.
4. Interconnection Architecture and Method of Assessing Interconnection Architecture, C.K. Cheng, R. Graham, E. Cheng, H. Chen. B. Yao, US Patent 7,622,779, 11/24/2009.
5. Efficient Transistor Level Simulation Using Two-Stage Newton-Raphson and Multigrid Method, C.K. Cheng and Zhengyong Zhu, US Patent 7,555,416, 7/30/2009.
6. Circuit Network Analysis using Algebraic Multigrid Approach, C.K. Cheng and Z. Zhu, US Patent 7,765,497, 7/27/2010.
7. Circuit Splitting in Analysis of Circuits at Transistor Level C.K. Cheng, R. Shi, and Z. Zhu, US Patent 8,020,122, 9/13/2011.
8. High Speed Clock Distribution Transmission Line Network, C.K. Cheng and H. Chen, US Patent 7,679,416, 3/16/2010.
9. Differential Transmission Line Having a Plurality of Leakage Resistors Spaced Between the Transmission Line, CK Cheng and H. Chen, US Patent 8,063,713, 11/22/2011.