cse290arch: Architecture Seminar

EBU3B 4140
Thursdays 11:30-12:20
Winter 2011

Course Description

The primary objective of the architecture seminar is to keep us abreast of interesting developments in architecture research with relatively little effort.

Each week everyone reads a paper and one or two students present it. Presentations are low-key:

Students can choose to present one of the papers listed below, a paper not on the list, or use the time to present their own work/prepare for an upcoming talk (research exam, thesis proposal, etc.).

Questions? Email jsampson at cs.ucsd.edu .


Schedule

Date Presenter Paper/Topic
January 6 Jack Sampson Introduction and initial paper assignments
January 6 Adrian Caulfield Moneta (slides)
January 13 Trevor Bunker Erasing Core Boundaries for Robust and Configurable Performance (slides)
January 20 Jack Sampson Efficient Complex Operators for Irregular Codes (slides)
January 27 Hung-Wei Tseng Data-Triggered Threads: Eliminating Redundant Computation (slides)
February 3 Leo Porter Fast Thread Migration via Cache Working Set Prediction (slides)
February 10 Michael Wei Reliably Erasing Data From Flash-Based Solid State Drives (slides)
February 17 Vasileios Kontorinis A Predictive Model for Dynamic Microarchitectural Adaptivity Control (slides)
February 24 Md. Kamruzzaman Inter-core Prefetching for Multicore Processors Using Migrating Helper Threads (slides)
March 3 Joel Coburn NV-Heaps: Making Persistent Objects Fast and Safe with Next-Generation, Non-Volatile Memories (slides)
March 10 Cancelled due to grad visit day

Papers

This quarter the papers are primarily from the previous MICRO (2010), and upcoming HPCA (2011) and ASPLOS(2011) conferences, although unselected papers from previous quarters also appear below.

MICRO 2010

Concurrency and Transactional Systems

Scalable Speculative Parallelization on Commodity Clusters Hanjun Kim, Arun Raman, Feng Liu (Princeton University), Jae W. Lee (Parakinetics), David I. August (Princeton University)

Hardware Support for Relaxed Concurrency Control in Transactional memory Systems Utku Aydonat, Tarek Abdelrahman (University of Toronto)

A Dynamically Adaptable Hardware Transactional Memory" Marc Lupon (UPC), Grigorios Magklis, Antonio Gonzalez (Intel and UPC)

ASF: AMD64 Extension for Lock-free Data Structures and Transactional Memory Jaewoong Chung, Luke Yen, Stephan Diestelhorst, Martin Pohlack, Michael Hohmuth (AMD), Dan Grossman (University of Washington), David Christie (AMD)

InstantCheck: Checking the Determinism of Parallel Programs Using On-the-fly Incremental Hashing Adrian Nistor, Darko Marinov, Josep Torrellas (University of Illinois at Urbana-Champaign)

Tolerating Concurrency Bugs Using Transactions as Lifeguards Jie Yu, Satish Narayanasamy (University of Michigan)

Architectural support for Fair Reader-Writer Locking Enrique Vallejo, Ramon Beivide (University of Cantabria), Adrian Cristal (Barcelona Supercomputing Center), Tim Harris (Microsoft Research Cambridge), Fernando Vallejo (University of Cantabria), Osman Unsal (Barcelona Supercomputing Center), Mateo Valero (Barcelona Supercomputing Center and UPC)

AtomTracker: A Comprehensive Approach to Atomic Region Inference and Violation Detection Abdullah Muzahid (University Of Illinois at Urbana-Champaign), Norimasa Otsuki (Renesas Electronics Corp), Josep Torrellas (University Of Illinois at Urbana-Champaign)

Reliability/Scheduling

Combating Aging with the Colt Duty Cycle Equalizer Erika Gunadi, Abhishek A. Sinkar, Nam Sung Kim, Mikko Lipasti (University of Wisconsin)

SAFER: Stuck-At-Fault Error Recovery for Memories Nak Hee Seong, Dong Hyuk Woo (Georgia Institute of Technology), Vijayalakshmi Srinivasan, Jude A. Rivers (IBM Research), Hsien-Hsin S. Lee (Georgia Institute of Technology)

AVF Stressmark: Towards an Automated Methodology for Bounding the Worst-case Vulnerability to Soft Errors Arun Arvind Nair, Lizy Kurian John (University of Texas at Austin), Lieven Eeckhout (Ghent University)

Flexible and Efficient Instruction-Grained Run-Time Monitoring Using On-Chip Reconfigurable Fabric Daniel Y Deng, Daniel Lo, Greg Malysa, Skyler Schneider, G. Edward Suh (Cornell University)

Memory Latency Reduction via Thread Throttling Hsiang-Yun Cheng, Chung-Hsiang Lin (National Taiwan University), Jian Li (IBM Austin Research Laboratory), Chia-Lin Yang (National Taiwan University)

Thread Cluster Memory Scheduling: Exploiting Differences in Memory Access Behavior Yoongu Kim, Michael Papamichael, Onur Mutlu, Mor Harchol-Balter (Carnegie Mellon University)

Voltage Smoothing: Characterizing and Mitigating Voltage Noise in Production Processors via Software-guided Thread Scheduling Vijay Janapa Reddi, Svilen Kanev, Wonyoung Kim, Simone Campanoni, Michael D. Smith, Gu-Yeon Wei, David Brooks (Harvard University)

Task Superscalar: An Out-of-Order Task Pipeline Yoav Etsion, Felipe Cabarcas, Alejandro Rico (BSC), Alex Ramirez (BSC and UPC), Rosa M. Badia (BSC), Eduard Ayguade (BSC and UPC), Jesus Labarta (BSC and UPC), Mateo Valero (BSC and UPC)

Memory and Caching

Parichute: Generalized Turbocode-Based Error Correction for Near-Threshold Caches Timothy Miller, James Dinan, Renji Thomas, Bruce Adcock, Radu Teodorescu (The Ohio State University)

Understanding the Energy Consumption of Dynamic Random Access Memories Thomas Vogelsang (Rambus Inc.)

Elastic Refresh: Techniques to Mitigate Refresh Penalties in High Density Memory Jeffrey Stuecheli (University of Texas Austin/IBM Austin), Dimitris Kaseridis (University of Texas Austin), Hillery Hunter (IBM Watson), Lizy John (University of Texas Austin)

Achieving Non-Inclusive Cache Performance with Inclusive Caches Aamer Jaleel, Eric Borch, Malini Bhandaru, Simon Steely Jr., Joel Emer (Intel)

Spatiotemporal Management of Capacity for Intra-Core Last Level Caches Dongyuan Zhan, Hong Jiang, Sharad C. Seth (University of Nebraska at Lincoln)

Sampling Dead Block Prediction for Last-Level Caches Samira M. Khan, Yingying Tian (The University of Texas at San Antonio), Daniel A. Jimenez (The University of Texas at San Antonio / Barcelona Supercomputing Center)

The ZCache: Decoupling Ways and Associativity Daniel Sanchez, Christos Kozyrakis (Stanford University)

Data Parallelism

Efficient Selection of Vector Instructions using Dynamic Programming Rajkishore Barik, Jisheng Zhao, Vivek Sarkar (Rice University)

Many-Thread Aware Prefetching Mechanisms for GPGPU Applications Jaekyu Lee, Nagesh B. Lakshminarayana, Hyesoon Kim, Richard Vuduc (Georgia Institute of Technology)

Single-chip Heterogeneous Computing: Does the future include Custom Logic, FPGAs, and GPUs? Eric S. Chung, Peter A. Milder, James C. Hoe, Ken Mai (Carnegie Mellon University)

Dynamic Thread Creation for Improving Processor Utilization on SIMT Streaming Processor Architectures Michael Steffen, Joseph Zambreno (Iowa State University)

Microarchitecture

Register Cache System not for Latency Reduction Purpose Ryota Shioya (University of Tokyo), Kazuo Horio (Fujitsu Laboratories Ltd.), Masahiro Goshima, Shuichi Sakai (University of Tokyo)

Synergistic TLBs for High Performance Address Translation in Chip Multiprocessors Shekhar Srikantaiah, Mahmut Kandemir (The Pennsylvania State University)

Erasing Core Boundaries for Robust and Configurable Performance Shantanu Gupta, Shuguang Feng, Amin Ansari, Scott Mahlke (University of Michigan)

Minimal Multi-Threading: Finding and Removing Redundant Instructions in Multi-Threaded Processors Guoping Long (Institute of Computing Technology, Chinese Academy of Sciences), Diana Franklin, Susmit Biswas, Pablo Ortiz (Universit of California, Santa Barbara), Jason Oberg (University of California, San Diego), Dongrui Fan (Institute of Computing Technology, Chinese Academy of Sciences), Frederic T. Chong (University of California, Santa Barbara)

A Predictive Model for Dynamic Microarchitectural Adaptivity Control Christophe Dubach, Timothy M. Jones (University of Edinburgh), Edwin V. Bonilla (Australian National University), Michael F.P. O'Boyle (University of Edinburgh)

ReMAP: A Reconfigurable Heterogeneous Multicore Architecture Matthew A. Watkins, David H. Albonesi (Cornell University)

Probabilistic Distance-based Arbitration: Providing Equality of Service for Many-core CMPs Michael Lee, John Kim (KAIST), Dennis Abts, Mike Marty (Google), Jae Lee (Parakinetics)

NoCs

Pseudo-Circuit: Accelerating Communication for On-Chip Interconnection Networks Minseon Ahn, Eun Jung Kim (Texas A&M University)

LOFT: A High Performance Network-on-Chip Providing Quality-of-Service Support Jin Ouyang, Yuan Xie (The Pennsylvania State University)

Throughput-Effective On-Chip Networks for Manycore Accelerators Ali Bakhoda (University of British Columbia), John Kim (KAIST), Tor M. Aamodt (University of British Columbia)

Adaptive Flow Control for Robust Performance and Energy Syed Ali Raza Jafri, Yu-Ju Hong, Mithuna Thottethodi, T. N. Vijaykumar (Purdue University)

Coherence

ScalableBulk: Scalable Cache Coherence for Atomic Blocks in a Lazy Environment Xuehai Qian, Wonsun Ahn, Josep Torrellas (University of Illinois, Urbana-Champaign)

Virtual Snooping: Filtering Snoops in Virtualized Multi-cores Daehoon Kim, Hwanju Kim, Jaehyuk Huh (KAIST)

Fractal Coherence: Scalably Verifiable Cache Coherence Meng Zhang, Alvin R. Lebeck, Daniel J. Sorin (Duke University)

Tools

Adaptive and Speculative Slack Simulations of CMPs on CMPs Jianwei Chen (ORACLE), Lakshmi Kumar Dabbiru, Daniel Wong, Murali Annavaram, Michel Dubois (University Of Southern California)

SD3: A Scalable Approach to Dynamic Data-Dependence Profiling Minjang Kim, Hyesoon Kim (Georgia Tech), Chi-Keung Luk (Intel Corporation)

Automatic Parallelization in a Binary Rewriter Aparna Kotha, Kapil Anand, Mathew Smithson, Greeshma Yellareddy, Rajeev Barua (University of Maryland, College Park)




Unselected Papers From Previous Quarter

Compilers / Run-time Systems

ASPLOS 2010

A Real System Evaluation of Hardware Atomicity for Software Speculation, Naveen Neelakantam, David Ditzel and Craig Zilles (University of Illinois at Urbana-Champaign; Intel) PDF


Parallel Programming

ASPLOS 2010

CoreDet: A Compiler and Runtime System for Deterministic Multithreaded Execution, Tom Bergan, Owen Anderson, Joe Devietti, Luis Ceze and Dan Grossman (University of Washington) PDF

Respec: Efficient online multiprocessor replay via speculation and external determinism, Dongyoon Lee, Benjamin Wester, Kaushik Veeraraghavan, Satish Narayanasamy, Peter Chen and Jason Flinn (University of Michigan) PDF


Scheduling in Parallel Systems

ASPLOS 2010

Probabilistic Job Symbiosis Modeling for SMT Processor Scheduling, Stijn Eyerman and Lieven Eeckhout (Ghent University) PDF

Flexible Architectural Support for Fine-grain Scheduling, Daniel Sanchez, Richard Yoo and Christos Kozyrakis (Stanford University) PDF


Software Reliability / Debugging

MICRO 2009

Offline symbolic analysis for multi-processor execution replay, Dongyoon Lee, Mahmoud Said, Satish Narayanasamy, Zijiang Yang, Cristiano Pereira (University of Michigan / Western Michigan University / Intel) PDF


Hardware Power and Energy Efficiency

ASPLOS 2010

Characterizing Processor Thermal Behavior, Francisco J. Mesa-Martínez, Ehsan K. Ardestani and Jose Renau (University of California, Santa Cruz) PDF

ISCA 2010

Energy-performance tradeoffs in processor architecture and circuit design: a marginal cost analysis, Omid Azizi, Aqeel Mahesri, Benjamin C. Lee, Sanjay J. Patel, Mark Horowitz (Stanford University) PDF

Understanding sources of inefficiency in general-purpose chips, Rehan Hameed, Wajahat Qadeer, Megan Wachs, Omid Azizi, Alex Solomatnikov, Benjamin C. Lee, Stephen Richardson, Christos Kozyrakis, Mark Horowitz (Stanford University) PDF


Data Centers

ISCA 2010

Web search using mobile cores: quantifying and mitigating the price of efficiency, Vijay Janapa Reddi, Benjamin C. Lee, Trishul Chilimbi, Kushagra Vaid (Harvard University / Stanford University / Microsoft Research) PDF

Energy proportional datacenter networks, Dennis Abts, Michael R. Marty, Philip M. Wells, Peter Klausler, Hong Liu (Google Inc.) PDF


Security and Hardware Reliability

MICRO 2009

Execution leases: a hardware-supported mechanism for enforcing strong non-interference, Mohit Tiwari, Xun Li, Hassan M. G. Wassel, Frederic T. Chong, Timothy Sherwood (University of California, Santa Barbara) PDF

ASPLOS 2010

Orthrus: Efficient Software Integrity Protection on Multi-Cores, Ruirui Huang, Dan Deng and G. Edward Suh (Cornell University) PDF

Shoestring: Probabilistic Soft-error Resilience on the Cheap, Shuguang Feng, Shantanu Gupta, Amin Ansari and Scott Mahlke (University of Michigan) PDF

Virtualized and Flexible ECC for Main Memory, Doe Hyun Yoon and Mattan Erez (The University of Texas at Austin) PDF

ISCA 2010

IVEC: off-chip memory integrity protection for both security and reliability, Ruirui Huang, G. Edward Suh (Cornell University) PDF