- Developed an FPGA based real-time face detection system.
- Designed an architecture for face detection using Haar classifiers using Verilog HDL.
- Designed a down-sampling image with fixed window mask and an integral image window buffer using Verilog HDL.
- Implemented single and multiple parallel classifiers on a Virtex-5 FPGA which are capable of processing the image at speeds of up to 84 fps.
- Implemented a face detection system has up to 84× performance gain over an equivalent software implementation.

- Developed an FPGA and ARM based motion-vision integrated embedded system.
- Designed a multiple axis motion control system including velocity profile generation, interpolation, and PID control using VHDL.
- Designed a low-level image processing system including binary thresholding, morphology, and binary large object operation using VHDL.
- Designed an embedded system including operating system, user interface, and libaries.
- Implemented a motion-vision integrated embedded system on a Virtex-4 FPGA whic distinguishes objects in images obtained from a camera, selects each object by a touch-screen user interface, and draw the selected object on the paper by motion control of an x-y table.

- Developed hardware acceleration of visual tracking using color histograms for intelligent robots.
- Developed a real-time visual tracking system that can improve the performance of pattern matching.
- Designed a window based image processing structure to provide real-time visual tracking performance using VHDL.
- Designed an adaptive color histograms to provide adaptability to slow appearace changes using VHDL.
- Implemented visual tracking system on a Virtex-4 FPGA which is capable of processing the images (640×480 pixels) at speeds of up to 81 fps and has up to 540× performance gain over an equivalent software implementation.

- Developed hardware acceleration of active visual tracking using projection profile matching and a particle filter for intelligent robots.
- Designed a projection profile matching structure to compensate background motion of an active camera using VHDL.
- Designed a particle filter structure to track a moving object in the cluttered environment using VHDL.
- Implemented an active visual tracking system on a Virtex-II FPGA which tracks a moving object in the cluttered environment using an active camera in such a way to track a moving object for a longer time interval and over a wider space range.
- Implemented an active visual tracking system which is capable of processing the images (640×480 pixels) at speeds of up to 39 fps.

- Developed hardware acceleration of multiple objects tracking using priority based probabilistic data association particle filters for intelligent robots.
- Designed a priority based probabilistic data association structure to determine the association between the observations and objects using VHDL.
- Designed parallel particle filters structure to update the existing trackers with the new measurements after their association using VHDL.
- Implemented a multiple objects tracking system on a Virtex-II FPGA which tracks multiple objects in a cluttered environment simultaneously. It is capable of processing the images (640×480 pixels) at speeds of up to 56 fps.

- Developed hardware acceleration of histogram equalization with automatic gain control for image enhancement.
- Designed an automatic gain control structure to stretch the dynamic range of the image to the whole gray level range using VHDL.
- Designed a histogram equalization structure to enhance the image contrast after automatic gain control using VHDL.
- Implemented a histogram equalization system with automatic gain control on a Virtex-II FPGA which is capable of processing the images (640×480 pixels) at speeds of up to 122 fps and has up to 12× and 129 × performance gains over an equivalent software implementation on Pentium 4 and PXA270 processors respectively.

- Developled FPGA based multiple axis motion control system for robotic manipulators.
- Designed linear, smooth, sinusoidal, asymmetric, and arbitrary velobity profiles generation using VHDL.
- Designed various interpolation including line, circle, arch, and spline using VHDL.
- Designed kinematics and inverse-kinematics usign VHDL.
- Designed PID closed loop control with feedback counters using VHDL.
- Designed various motor drivers including step, AC, and DC motors (2-channel, 16-bit digital, PWM).
- Implemented a multiple axis motion contol system on a Virtex-II FPGA that generates various velocity profiles, performs various interpolation, performs kinematics and inverse-kinematics, and communicates to host PC through PCI bus.

- Developled FPGA based motion control chip to generate various velocity profiles for motors.
- Designed linear, smooth, sinusoidal, asymmetric, and arbitrary velobity profiles generation using VHDL.
- Designed PID closed loop control with feedback counters using VHDL.
- Designed PCI interface to communicate to host PC
- Im plemented a motion control chip on a Spartan-IIE FPGA to generate velocity profiles of desired characteristics according given tasks.

- Designed an open architecture motion controller using a TMS320C6711 DSP.
- Implemented a system that has an open architecture including IEEE-NEMI based motion libraries, flexible library functions, and flexible GUI menus, generates linear, smooth, sinusoidal, asymmetric, and arbitrary velocity profiles, performs various interpolation including line, circle, arch, and spline, performs kinematics and inverse-kinematics, performs PID control with feedback counters, and has step, AD, DC motor drivers.