Are AES x86 Cache Timing Attacks Still Feasible? (Short Paper)

By Keaton Mowery, Sriram Keelveedhi, and Hovav Shacham.

In Proceedings of CCSW 2012. ACM Press, Oct. 2012. To appear.


We argue that five recent software and hardware developments—the AES-NI instructions, multicore processors with per-core caches, complex modern software, sophisticated prefetchers, and physically tagged caches—combine to make it substantially more difficult to mount data-cache side-channel attacks on AES than previously realized. We propose ways in which some of the challenges posed by these developments might be overcome. We also consider scenarios where side-channel attacks are attractive, and whether our proposed workarounds might be applicable to these scenarios.



@InProceedings{MKS12, author = {Keaton Mowery and Sriram Keelveedhi and Hovav Shacham}, title = {Are {AES} {x86} Cache Timing Attacks Still Feasible? (short paper)}, booktitle = {Proceedings of CCSW 2012}, year = 2012, editor = {Srdjan Capkun and Seny Kamara}, month = oct, publisher = {ACM Press} }

Navigation: Hovav Shacham // Publications // [MKS12]