Hao Zhuang

Research and Working Experience

Industry/Research Labs

  • Google, Mountain View, CA, USA. (2018.07-)
    Software Engineer

  • ANSYS, Inc., San Jose, CA, USA. (2015.06-2018.07)
    ANSYS, Inc.: The leading engineering simulation software (computer-aided engineering) company, which provides simulation technologies for designs of automobile, Internet of things, VLSI chip/architecture, and high perfomance computing, etc. Our Ansys Apache unit also works on "Big Data for chip designs".
    Senior Software Developer, 2016.09-2018.07
    Software Developer II, 2015.10-2016.09
    Software Engineer Intern, 2015.06-2015.09
    - Worked on EDA and CAD software for design automation for computing systems/VLSI using applied machine learning, numerical algorithms and simulation. Applied to timing analysis, dynamic voltage drop, power/EM analysis, and RTL optimization.
    - Designed time integration algorithms, numerical and matrix solvers, and the corresponding software architecture for the industrial standard ANSYS Apache RedHawk, and the latest Compute Platform RedHawk-SC at SeaScape.
    - Designed the Chip Power Model integration in the latest production line for Reliable Automotive, Mobile And HPC Electronic Designs [news].
    - Delivered enhanced features in Totem and Pathfinder.
    - Conducted research for ANSYS big data and machine learning platform SeaScape.

  • Synopsys, Inc., Mountain View, CA, USA. (2014.06-2014.09)
    Synopsys, Inc.: The leading software and IP company in Electronic Design Automation (EDA). Products contain IC Compiler, PrimeTime, Design Compiler, Coverity, etc.
    Software Engineer Intern
    - Delivered two critical performance improvements (programming and algorithimic aspects) on multi-thread programming and matrix solver in network rail & power analysis engine (now with PrimeTime team, the de facto timing analysis tool in the market).

  • QUALCOMM Research & UCSD JSOE, San Diego, CA, USA. (2013.06-2014.06)
    Qualcomm, Inc.: A global semiconductor company for wireless telecommunications products and services.
    FMA Researcher in VLSI ASIC & Electornic Design Automation, funded by Qualcomm FMA Fellowship.
    - Designed high peformance adders/shifters for computer architecture in 3D-ICs;
    - Conducted research on 3D-ICs Global placement tools.

  • TNList (Tsinghua National Lab for Information Science and Technology), Beijing, China. (2012.04-2012.07)
    Research Intern
    - Developed EDA software, a multithreaded VLSI interconnect capacitance extraction program RWCap (parallel programming via pthread) and RWCap-GPU (parallel programming via GPU).
    - Filed two patents.


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