Hao Zhuang, Ph.D.
I earned my Ph.D. degree in Computer Science from University of California, San Deigo, CA, USA (UCSD) in 2016 after 3-year full-time PhD training. I published 15 peer-reviewed papers during this period and had around 210 paper citations by the graduation. My graduate research included numerical algorithms, matrix computation, and stochastic numerical solvers, with the applications in the analysis of large-scale dynamical systems, computer-aided design, and design automation for building computer chips. Some of the techniques I developed during my graduate research had been adopted in the industry. Generally, I am interested in computational mathematics, numerical algorithms, high-performance computing (HPC) and distributed computing systems for optimization, signal processing, large-scale dynamical systems analysis. Beyond building computation engines for design automation tools of VLSI chips, I also contributed to the projects, which make education massive and accessible to the world by the techniques from natural language processing, computational linguistics, machine learning, numerical algorithms and matrix computation.
I am now a Senior Software Developer at ANSYS, Inc. to commercialize my research at graduate schools. Since June 2015, I write software at ANSYS Apache and build distributed computation infrastructure, large-scale matrix computation algorithms, machine learning systems, and big data applications. The products are used for power analysis and verification of tape-outs of modern low power CPU, GPU, and ASIC, which are used by different purposes of computing, such as general logic operations, deep learning, big data processing, data center traffic, etc. It is my privilege to work with the R&D teams consist of legends in the area of design automation algorithms, such as the forerunner and researchers of AWE, the creators of MIT FastCap, CMU PRIMA, UT RICE, Synopsys PrimeTime and Apache Redhawk. Before that I worked at Synopsys, Inc., designing graph partitioning algorithms and multi-threaded programs to scale up the matrix solver for full-chip power network analysis with over billion graph nodes.
Selected Publications [full list] [Google scholar citations]
Selected Patent [full list]
Industrial Experience [details]
Academic Experience [details]
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