Computer Science & Engineering Department,
University of California, San Diego, CA, USA
Mailing: 9500 Gilman Dr., EBU3, CSE Dept., La Jolla, CA, 92093-0404
E-mail: zhuangh [at] ucsd.edu
Google Scholar Profile and
Design automation for digitial systems,
circuits, VLSI CAD;
design automation and verification algorithms, numerical methods,
matrix exponential operator, power/timing verification and simulation,
high performance computing, scalable distributed/parallel programming,
software design, data structure, computer architecture
June. 2014: (1) Attended ACM/IEEE DAC 2014, and gave a talk. (2) Passed UCSD CSE Ph.D's research exam (Committee members: Prof. Steven Swanson (chair), Prof. Sanjoy Dasgupta, and Prof. Lawrence Saul). (3) Started internship at Synopsys R&D at the end of month.
Feb. 2014: One paper got accepted by the top-tier ACM/IEEE Design Automation Conference (DAC) 2014, San Francisco, CA, thanks my co-authors, Dr. S.-H. Weng (now a research scientist with Facebook, Inc.) and J.-H. Lin, and Prof. C. K. Cheng.
Dec. 2013: Gave a talk on matrix exponential based circuit simulation in EDA Lab, Tsinghua University, hosted by Prof Wenjian Yu.
May 2013: Our lab is awarded with Qualcomm FMA Fellowship.
Sep. 2012: Then, joined Computer Science & Engineering Department, University of California, San Diego, CA.
Jul. 2012: Graduated from Peking University, Beijing, China, and finished the joint research work with Tsinghua University.
Feb. 2012: Be awarded with Charles Lee Powell Fellowship.
Research and Working Expeirence
Synopsys, Inc., Mountain View, CA (R&D Technical Intern, 2014.06-)
Department of Computer Science and Engineering, University of California, San Diego, CA (Research Assistant, 2012.09-present)
Qualcomm Research, San Diego, CA (FMA Student Researcher, 2013.06-2014.06)
TNList (Tsinghua National Lab for Information Science and Technology), Beijing, China (Summer Intern, 2012.04-2012.07)
EDA Lab, Department of Computer Science and Technology, Tsinghua University, Beijing, China (Research Assistant, 2011.01-2012.03)
TSRC Lab, School of EECS, Peking University, Beijing, China (Research Assistant, 2008.10-2012.07)
Algorithms, mathematical models in circuit simulation, timing and power analysis, placement.
Design automation for digital systems.
Distributed and Scalable software/algorithm as well as programming language for multicore/manycore computers, high perforamnce computing (HPC).
Overall, building high performance computing systems for VLSI CAD.
RWCap: a multi-threaded 3-D floating random walk algorithm based capacitance solver for VLSI Parastic extraction (Implementation using C++, and POSIX pthread)
Contributors: Hao Zhuang, Chao Zhang, Gang Hu, Kuangya Zhai, Zhi Liu, Ting Dai. Supervisor: Wenjian Yu.
Contributors: Chao Zhang, Hao Zhuang. Supervisor: Wenjian Yu
Please check Prof. Wenjian Yu's page for the latest updates.
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(Top-tier and good conferences: DAC, ICCAD and DATE, ASP-DAC)
Hao Zhuang, Shih-Hung Weng, Jeng-Hau Lin, Chung-Kuan Cheng, “MATEX: A Distributed Framework for Transient Simulation of Power Distribution Networks,” Proc. ACM/EDAC/IEEE Design Automation Conference (DAC), June 2014. [pdf] [slides] [poster] (acceptance rate: 22.1%, 174/787)
Hao Zhuang, Shih-Hung Weng, Chung-Kuan Cheng, “Power Grid Simulation using Matrix Exponential Method with Rational Krylov Subspaces,” Proc. IEEE Intl. Conf. on ASIC (ASICON), 2013. Updated on [arXiv]
Hao Zhuang, Wenjian Yu, Gang Hu, Zhi Liu, Zuochang Ye, “Fast floating random walk algorithm for multi-dielectric capacitance extraction with numerical characterization of Green's functions,” in Proc. ACM/IEEE Asia & South Pacific Design Automation Conf. (ASP-DAC) , Sydney, Australia, Jan. 2012, pp. 377-382. [pdf]
Hao Zhuang, Wenjian Yu, Gang Hu, Zuochang Ye, “Numerical characterization of multi-dielectric Green's function for floating random walk based capacitance extraction,” Proc. IEEE Intl. Conf. ASIC (ASICON), Oct. 2011, pp. 361-364. [pdf] [slides]
Hao Zhuang, Jingwei Lu, Kambiz Samadi, Yang Du and Chung-Kuan Cheng, “Performance-Driven Placement for Design of Rotation and Right Arithmetic Shifters in Monolithic 3D ICs,” Proc. IEEE ICCCAS, 2013.
Kuangya Zhai, Wenjian Yu, Hao Zhuang, “GPU-Friendly floating random walk algorithm for capacitance extraction of VLSI interconnects,” in Proc. IEEE Design, Automation & Test in Europe (DATE) , Grenoble, France, Mar. 2013, pp. 1661-1666. [pdf]
(Top-tier journals: TCAD)
Wenjian Yu*, Hao Zhuang, Chao Zhang, Gang Hu, and Zhi Liu, “RWCap: A floating random walk solver for 3-D capacitance extraction of VLSI interconnects,” IEEE Trans. Computer-Aided Design (TCAD), 32(3): 353-366, 2013. listed as one of the TCAD popular papers and best paper award nomination
[pdf] [software package]
, *-Hao Zhuang's research advisor during this work.
Wenjian Yu, Kuangya Zhai, Hao Zhuang, Junqing Chen, “Accelerated floating random walk algorithm for the electrostatic computation with 3-D rectilinear-shaped conductors,” Simulation Modelling Practice and Theory, 34(5): 20-36, 2013. [pdf]
Circuit Simulation Algorithms and its Parallel/Distributed Processing, Applications of Power Network Analysis (Mar. 2013 - present)
Description: “To analyze and verify VLSI systems via full circuit simulation and to demonstrate vastly improved scalability in order to raise the quality and scope of predictive circuit modeling. VLSI circuit simulation has become critical due to interconnect dominance of advanced fabrication technologies. Functional modules are integrated through substrates and connected by wires with parasitics. A simulation of the whole system will empower designers with a full grasp of the transient behavior of the circuits.”
Keywords: Matrix Exponential, Krylov Subspace, Distributed Computing, Paralel Computing, VLSI Design and Analysis,
Numerical Algorithms, Differential Equations, Compact Modeling, GPU, Power Distribution Network,
Automated source code re-engineering for disruptive technologies (Feb. 2014)
Keywords: novel translation algorithms and run time support, MPI, OpenMP, CUDA, Manycores.
Design and Design Automations in Placement, Synthesis of 2D/3D-ICs (Jun. 2013 - present)
Description: “To investigate the floorplanning and bus synthesis for three-dimensional integrated circuits. The goal is to extract and manipulate the topology of 3D geometry for physical layout.”
Keywords: Computer Architecture, Interconnect Network, Physical Design, Placement, Linear and Nonlinear Programming, Combinatorial Optimization, VLSI Design, VLSI Synthesis
Stochastic Algorithms for VLSI chip parasitic extraction field solver (Feb. 2011 - Jul. 2012)
Description: To extract capacitance parameters in VLSI design by devising floating random walk algorithms. This method bares improved scalability and efficiency for large scale problem. Some pratical software packages have been prototyped, which can be found in Sec. Software on this page. [link]
Keywords: Floating Random Walk Algorithms, Multi-thread Programming, GPU, 3D Space Management, Importance/Stratified Sampling, Monte Carlo Algorithm
My education background dangles in EECS and Applied Math.
Thanks to the people around in CS/EE/Math departments and even my roommates, who bring to me the beauty of theoritical parts
of kernel solvers, numerical solvers, optimizers, machine learning as well as their applications on computer systems designs, programming.