Research Interests & Projects
My current interests:
Algorithms, mathematical models in interconnect network design, physical design, synthesis, circuit simulation, timing and power analysis.
Circuit Simulation Algorithms and its Parallel/Distributed Processing, Applications of Power Network Analysis (Mar. 2013 - present)
Description: “To analyze and verify VLSI systems via full circuit simulation and to demonstrate vastly improved scalability in order to raise the quality and scope of predictive circuit modeling. VLSI circuit simulation has become critical due to interconnect dominance of advanced fabrication technologies. Functional modules are integrated through substrates and connected by wires with parasitics. A simulation of the whole system will empower designers with a full grasp of the transient behavior of the circuits.”
Keywords: Computer Architecture, VLSI Design and Analysis,
Numerical Algorithms, Differential Equations, Compact Modeling, GPU, Power Distribution Network,
Stay tuned: some opensource code and package will be released.
Design and Design Automations in Placement, Synthesis of 2D/3D-ICs (Jun. 2013 - present)
Description: “To investigate the floorplanning and bus synthesis for three-dimensional integrated circuits. The goal is to extract and manipulate the topology of 3D geometry for physical layout.”
Keywords: Computer Architecture, Interconnect Network, Physical Design, Placement, Linear and Nonlinear Programming, Combinatorial Optimization, VLSI Design, VLSI Synthesis
Stochastic Algorithms for VLSI chip parasitic extraction field solver (Feb. 2011 - Jul. 2012)
Description: To extract capacitance parameters in VLSI design by devising floating random walk algorithms. This method bares improved scalability and efficiency for large scale problem. Some pratical software packages have been prototyped, which can be found in Sec. Software on this page. [link]
Keywords: Floating Random Walk Algorithms, Multi-thread Programming, GPU, 3D Space Management, Importance/Stratified Sampling, Monte Carlo Algorithm
My education background dangles in EECS and Applied Mathemetics.
Thanks to my advisors, colleages and professors in CS/EE/Math departments and even my roommates, who bring to me the beauty of theoritical parts
of kernel solvers,
machine learning as well as their applications on computer systems designs, programming.
Hao Zhuang, Wenjian Yu, Gang Hu, Zuochang Ye, “Numerical characterization of multi-dielectric Green’s function for floating random walk based capacitance extraction,” Proc. IEEE Intl. Conf. ASIC (ASICON), Xiamen, China. Oct. 2011, pp. 361-364. [pdf]
Hao Zhuang, Wenjian Yu, Gang Hu, Zhi Liu, Zuochang Ye, “Fast floating random walk algorithm for multi-dielectric capacitance extraction with numerical characterization of Green's functions,” in Proc. ACM/IEEE Asia & South Pacific Design Automation Conf. (ASP DAC) , Sydney, Australia, Jan. 2012, pp. 377-382. [pdf]
Wenjian Yu, Hao Zhuang, Chao Zhang, Gang Hu, and Zhi Liu, “RWCap: A floating random walk solver for 3-D capacitance extraction of VLSI interconnects,” IEEE Trans. Computer-Aided Design (TCAD), 32(3): 353-366, 2013. [pdf]
Kuangya Zhai, Wenjian Yu, Hao Zhuang, “GPU-Friendly floating random walk algorithm for capacitance extraction of VLSI interconnects,” in Proc. IEEE Design, Automation & Test in Europe (DATE) , Grenoble, France, Mar. 2013, pp. 1661-1666. [pdf]
Wenjian Yu, Kuangya Zhai, Hao Zhuang, Junqing Chen, “Accelerated floating random walk algorithm for the electrostatic computation with 3-D rectilinear-shaped conductors,” Simulation Modelling Practice and Theory, 34(5): 20-36, 2013. [pdf]
Hao Zhuang, Shih-Hung Weng, Chung-Kuan Cheng, “Power Grid Simulation using Matrix Exponential Method with Rational Krylov Subspaces,” Proc. IEEE Intl. Conf. on ASIC (ASICON), 2013. [arXiv]
Hao Zhuang, Jingwei Lu, K. Samadi, Y. Du and C.K. Cheng, “Performance-Driven Placement for Design of Rotation and Right Arithmetic Shifters in Monolithic 3D ICs,” Proc. IEEE ICCCAS, 2013. (to appear)
RWCap: a 3-D floating random walk based capacitance solver for VLSI Parastic extraction (Implementation using C++)
Contributors: Hao Zhuang, Chao Zhang, Gang Hu, Kuangya Zhai, Zhi Liu, Ting Dai. Supervisor: Wenjian Yu.
Contributors: Chao Zhang, Hao Zhuang. Supervisor: Wenjian Yu
May 2013: Be awarded with Qualcomm FMA Fellowship. Thanks to Jingwei Lu, CK Cheng, and Kambiz Samadi, Yang Du.
Sep. 2012: Then, joined Computer Science & Engineering Department, University of California, San Diego, CA.
Jul. 2012: Graduated from Peking University, Beijing, China, and finished the joint research work with Tsinghua University, thanks to Prof. Wenjian Yu.
Feb. 2012: Be awarded with Charles Lee Powell Fellowship.