Hao Zhuang, Ph.D. Computer Science @ UCSD

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Hao Zhuang
Ph.D. in Computer Science,
University of California, San Diego, CA, USA.

Contact: zhuang.howard [at] gmail.com | hao.zhuang [at] cs.ucsd.edu

google scholar | linkedin

Research Interests:

My current interests are design methodologies and automation for computing systems, computer architecture, and accelerators for machine learning/deep learning, video codec/image processing/computer vision, and numerical algorithms.

Graduate Schools:

I got my Ph.D. degree in Computer Science from University of California, San Deigo, CA, USA (UCSD) in 2016. My graduate research projects included numerical algorithms, matrix computation, and stochastic algorithms with the applications in the analysis of large-scale dynamical systems from VLSI/ASIC chips/computer achitectures, design automation and computer-aided design (EDA/CAD) for building computers and chips. Some of the techniques I developed with my colleagues during my graduate research (both my master and PhD) had been commercialized or purchased by the industry. My PhD course concentration is Computer Systems.


[Google] I am a Software Engineer working on software and hardware at Google, Mountain View, CA, USA.

[ANSYS, Apache] Before Google, I was a Senior Software Developer at ANSYS Semiconductor Business Unit, formerly Apache Design Solutions Inc (a startup acquired by ANSYS) for 3 years. I worked on Design Automation (EDA/VLSI CAD) research using numerical algorithms, machine Learning, and distributed computing for circuit-level, gate/RTL-level simulation to provide the industrial standard ASIC, VLSI chip power sign-off software. The products have been used over a decade for taping out CPU, GPU, and AI chips. My role was to lead and architect the machine learning-assisted products (for chip timing, dynamic voltage drops, power/EM, and RTL optimizations) in Semiconductor Business Unit on top of the big data distributed system product.

(1) For simulation solver in the flagship product ANSYS RedHawk, I mainly worked with Senior Software Architect Dr. Steven P. McCormick (MIT EECS PhD’89), who was one of pioneers in VLSI model order reduction research. (2) To solve challenging machine learning problems in design automation, I worked with Chief Technologiest and Apache co-founder Dr. Norman Chang (UC Berkeley EECS PhD’90). (3) I also worked on the parasitic extraction, circuit graph network reductions, model order reduction Chip Power Model integration in the latest production line for Automotive, Mobile and HPC Electronic Designs. It was my privilege to work with the teams consist of legends in the area of design automation research, such as the researcher of AWE, the creators of MIT FastCap, CMU PRIMA, UT RICE, Synopsys PrimeTime, and Apache Redhawk.

[Synopsys] Before ANSYS Apache, I wroted software at Synopsys Inc as an summer intern in 2014, working on graph partitioning algorithm and its multi-threaded programs. The algorithm I help developed in that summer scaled up the matrix solver for full-chip power network analysis with over billion graph nodes.

[Qualcomm Research] While my PhD research, I was also with Qualcomm Research as one of FMA fellows and worked on low-power datapath synthesis, computer architecture, and 3D-ICs.


I believe the technologies play the essential role for the education and society, I am also a user of MIT OpenCourseWare, Udacity, and Coursera. During the spare time of my PhD study, I helped some online education projects, such as online collaboration and personalized learning systems, in order to make education massive and accessible to the world. I worked with linguists, teachers, and professors, used natural language processing, computational linguistics, distributed systems.

I got married to Xiao Liu, who can jump way farther than me. She was a national college track and field athlete, and represented China and Peking University for International 2007, 2009 (final 8th place), 2011 Summer Universiade. I am a fan of NBA and play basketball games weekly, usually (position) 2 on the court.

Selected Publications [Full List] [Google Scholar Citations]

Selected Software Packages [Full List]

  • RWCap: a multi-threaded 3-D floating random walk algorithm based capacitance solver for ASIC, VLSI Parastic extraction (Implementation using C++, and POSIX pthread). Please check Prof. Wenjian Yu's page for the latest updates.

Selected Patent [Full List]



  • Qualcomm FMA Fellowship (2013-2014): one of the four recipients [award].

  • Charles Lee Powell Fellowship (2012-2015): for supporting outstanding PhD engineering students.

  • Peking University Wu-Si Scholarship (2011).

Industrial Experience [Details]

Academic Experience [Details]

Selected Talks [Full List]

  • “Matrix Exponential Integration in Time-domain Analysis of Circuit Simulation,” at ECE Department, Peking University, China, Oct 2015 [Flyer]

  • “Matrix Exponential Integration in Time-Domain Analysis of Circuit Simulation,” at Department of Electrical and Electronics Engineering, The University of Hong Kong, Hong Kong, Oct. 2015

  • “Algorithms for Dynamic Power Grid Simulation Using Matrix Exponentials,” at ANSYS, Inc., San Jose, Sept. 2015.


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