Hao Zhuang, Ph.D. student in Computer Science + Computer Engineering.
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Computer Science & Engineering Department,
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Recent Highlights/Publications
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Conferences:
(Top-tier and good conferences: DAC, ICCAD and DATE, ASP-DAC)
(power delivery network, distributed computing algorithm, circuit simulation, matrix exponential, large scale computing) Hao Zhuang, Shih-Hung Weng, Jeng-Hau Lin, Chung-Kuan Cheng, “MATEX: A Distributed Framework for Transient Simulation of Power Distribution Networks,” Proc. ACM/EDAC/IEEE Design Automation Conference (DAC), June 2014. [pdf] [slides] [poster] (acceptance rate: 22.1%, 174/787)
(chip interconnect, extraction and modeling, random algorithm, multithreaded programming) Hao Zhuang, Wenjian Yu, Gang Hu, Zhi Liu, Zuochang Ye, “Fast floating random walk algorithm for multi-dielectric capacitance extraction with numerical characterization of Green's functions,” in Proc. ACM/IEEE Asia & South Pacific Design Automation Conf. (ASP-DAC), Jan. 2012, pp. 377-382. [pdf] (acceptance rate: 34%, 99/288)
(chip interconnect, extraction and modeling, GPU computing) Kuangya Zhai, Wenjian Yu, Hao Zhuang, “GPU-Friendly floating random walk algorithm for capacitance extraction of VLSI interconnects,” in Proc. IEEE Design, Automation & Test in Europe (DATE), Mar. 2013, pp. 1661-1666. [pdf] (acceptance rate: 36%)
(power delivery network, circuit simulation, numerical algorithm) Hao Zhuang, Shih-Hung Weng, Chung-Kuan Cheng, “Power Grid Simulation using Matrix Exponential Method with Rational Krylov Subspaces,” Proc. IEEE Intl. Conf. on ASIC (ASICON), 2013. Updated on [arXiv] [pdf] [slides]
(chip interconnect, extraction and modeling, random algorithm, field solver) Hao Zhuang, Wenjian Yu, Gang Hu, Zuochang Ye, “Numerical characterization of multi-dielectric Green's function for floating random walk based capacitance extraction,” Proc. IEEE Intl. Conf. ASIC (ASICON), Oct. 2011, pp. 361-364. [pdf] [slides]
(VLSI placement, optimization algorithm, 3D-IC, low power design) Hao Zhuang, Jingwei Lu, Kambiz Samadi, Yang Du and Chung-Kuan Cheng, “Performance-Driven Placement for Design of Rotation and Right Arithmetic Shifters in Monolithic 3D ICs,” Proc. IEEE ICCCAS, 2013. [pdf] [slides]
Journals:
(Top-tier journals: TCAD)
(chip interconnect, extraction and modeling, statistical algorithm, random sampling) Wenjian Yu*, Hao Zhuang, Chao Zhang, Gang Hu, and Zhi Liu, “RWCap: A floating random walk solver for 3-D capacitance extraction of VLSI interconnects,” IEEE Trans. Computer-Aided Design (TCAD), 32(3): 353-366, 2013. listed as one of the TCAD popular papers and best paper award nomination 2014 [pdf] [software package]. *- Hao Zhuang (1st student author)'s research advisor during this work
(VLSI placement, optimization algorithm, FFT solver application) Jingwei Lu, Hao Zhuang, Pengwen Chen, Hongliang Chang, Chin-Chih Chang, Yiu-Chung Wong, Lu Sha, Dennis Huang, Yufeng Luo, Chin-Chi Teng, Chung-Kuan Cheng, “ePlace-MS: Electrostatics based Placement for Mixed-Size Integrated Circuits,”, IEEE Trans. Computer-Aided Design (TCAD) [Special Issues 2014] (to appear).
(chip interconnect, extraction and modeling, GPU computing) Wenjian Yu, Kuangya Zhai, Hao Zhuang, Junqing Chen, “Accelerated floating random walk algorithm for the electrostatic computation with 3-D rectilinear-shaped conductors,” Elsevier Simulation Modelling Practice and Theory, 34(5): 20-36, 2013. [pdf]
Patents
GPU-based system and method for extracting capacitance parameter of integrated circuit (pending) Jul 10, 2013
IC design calculation method based on extracting the capacitance parameter random walk Dec 11, 2013
Recent Software
RWCap: a multi-threaded 3-D floating random walk algorithm based capacitance solver for VLSI Parastic extraction (Implementation using C++, and POSIX pthread) Related Express
RWCap (v1)
Contributors: Hao Zhuang, Chao Zhang, Gang Hu, Kuangya Zhai, Zhi Liu, Ting Dai. Supervisor: Wenjian Yu.RWCap (v2)
Contributors: Chao Zhang, Hao Zhuang. Supervisor: Wenjian Yu
Please check Prof. Wenjian Yu's page for the latest updates.
Research Interests
Algorithms, mathematical models in circuit simulation, timing and power (delivery network) analysis, placement.
Design automation for digital systems, VLSI chip designs and computer architecture.
Building high/heterogeneous performance computing algorithms and systems for VLSI CAD as well as lower power computing computer architecture.
Matrix computations and statistical, random algorithmms, graph algorithms for scientific simulation, data, network analysis.
Computer system designs.
Keywords:
design automation for digital systems, circuits, VLSI CAD, low-power systems and energy-efficient computer architecture, design automation and verification algorithms, numerical methods, matrix exponential operator, power/timing verification and simulation, high performance computing, scalable distributed/parallel programming, software design, data structure
Some updates
Nov. 2014: (1) Our placement journal paper (ePlace) to IEEE TCAD got accepted; (2) Served as the computer system administrator at the VLSI design lab.
June 2014: (1) Attended ACM/IEEE DAC 2014, and gave a talk. (2) Passed UCSD CSE Ph.D's research exam (Committee members: Prof. Steven Swanson (chair), Prof. Sanjoy Dasgupta, and Prof. Lawrence Saul). (3) Started R&D technical internship at Synopsys, Inc., and to live at the campus of Stanford University at the end of month. (4) Gave a research talk at Synopsys, Inc.
Apr. 2014: Attend UC San Diego Jacob School of Engineering's Research Expo
Feb. 2014: One paper got accepted by the top-tier ACM/IEEE Design Automation Conference (DAC) 2014, San Francisco, CA, thanks my co-authors, Dr. S.-H. Weng (now a research scientist with Facebook, Inc.) and J.-H. Lin, and Prof. C. K. Cheng.
Dec. 2013: Gave a talk on matrix exponential based circuit simulation in EDA Lab, Tsinghua University, hosted by Prof Wenjian Yu.
May 2013: Our lab was awarded with Qualcomm FMA Fellowship.
Sep. 2012: Joined Computer Science & Engineering Department, University of California, San Diego, CA.
Jul. 2012: Graduated from Peking University, Beijing, China, and finished the joint research work with Tsinghua University.
Feb. 2012: Awarded with Charles Lee Powell Fellowship.
Research and Working Expeirence
Synopsys, Inc., Mountain View, CA (R&D Technical Intern, 2014.06-2014.09)
Department of Computer Science and Engineering, University of California, San Diego, CA (Research Assistant, 2012.09-present)
Qualcomm Research and UCSD JSOE, San Diego, CA (FMA Student Researcher, 2013.06-2014.06)
TNList (Tsinghua National Lab for Information Science and Technology), Beijing, China (Summer Intern, 2012.04-2012.07)
EDA Lab, Department of Computer Science and Technology, Tsinghua University, Beijing, China (Research Assistant, 2011.01-2012.03)
TSRC Lab, School of EECS, Peking University, Beijing, China (Research Assistant, 2008.10-2012.07)
Services
IEEE student memeber since 2011.
ACM student memeber since 2014.
SIAM student memeber since 2014.
External reviewer, ACM/IEEE Design Automation Conference (DAC).
External reviewer, ACM/IEEE International Symposium on Physical Design (ISPD).
Reviewer, IEEE Transaction on Computer Aided Design (TCAD).
Teaching
Assistant, CSE245: Numerical Algorithms and Circuit Simulation (2015 Winter)
Teaching Assistant, CSE140: Components and Design Techniques for Digital Systems (2014 Autumn)
-- Textbook: Digital Design and Computer Architecture (2nd Edition) by David Mooney Harris and Sarah L. Harris
Selected Courses
Computer Science (CS)
CSE202: Algorithms and Data Structures (Prof. Russell Impagliazzo)
-- Project: Cache-Oblivious Algorithm and Data Structures.CSE230: Programming Language (Prof. Ranjit Jhala)
-- Actually, it is a functional language course, talking about Haskell.
CSE231: Advanced Compilers (Prof. Sorin Lerner)
-- Final Project: Verilog Generation of Sub-Blocks within UCSD Conservation Cores Architecture (using LLVM, within Prof. Micheal Taylor's group).CSE240: Principles in Computer Architecture (Prof. Dean Tullsen)
-- Project 1: Branch Predictor Design and Simulation. -- Project 2: Cache Design and Simulation.CSE120: Principles of Operating Systems (Prof. Joseph Pasquale)
-- Have fun with xv6@MIT and qemu by self.CSE260: Parallel Computation (Prof. Scott Baden)
-- Final Project: Parallel Matrix Vector Multiplication using MPI.CSE223B: Distributed Computing and Systems (Prof. Alex Snoeren)
--Final Project (the top-ranked project in the class): Trusted Bridge - Online Distributed Synchronized Storage Systems (using C++, node.js, python), we wrote a simple online storage systems, also interacted with Dropbox API, Google Drive API for storage aggregations.
Mathematics
MATH270B: Numerical Approximation and Nonlinear Equations (Prof. Michael Holst)
MATH270C: Numerical Oridinary Equations (Prof. Melvin Leok)
-- Classical algorithms on differential equations.MATH: Real Analysis
-- Inspired by the understanding of Lebesbegue integration and statistical notion of integration, and apply importance sampling to RWCap.
Electrical Engineering (EE)
CSE245: Circuit Simulation (Prof. Chung-Kuan Cheng)
-- Final Project: Linear Circuit Simulation using Matrix Exponential Method with Rational Krylov Subspaces, which becomes a part of paper accepted by IEEE Intl. Conf. on ASIC 2013.CSE291: High Performance Interconnects (Prof. Chung-Kuan Cheng)
-- Seminar's topics on networks from data center servers wiring to on-chip interconnects.EECS: Semiconductor Device Physics and Fabrication Technologies (Prof. Ru Huang and Prof. Xing Zhang)
-- MOS Device physics and fabrications.EECS: Digital Circuits and Systems (Prof. Xiaoyan Liu)
-- Final Project: Adder Design and Optimization
Research Projects
Circuit Simulation Algorithms and its Parallel/Distributed Processing, Applications of Power Network Analysis (Mar. 2013 - present)
Description: “To analyze and verify VLSI systems via full circuit simulation and to demonstrate vastly improved scalability in order to raise the quality and scope of predictive circuit modeling. VLSI circuit simulation has become critical due to interconnect dominance of advanced fabrication technologies. Functional modules are integrated through substrates and connected by wires with parasitics. A simulation of the whole system will empower designers with a full grasp of the transient behavior of the circuits.” [link]
Keywords: Matrix Exponential, Krylov Subspace, Distributed Computing, Paralel Computing, VLSI Design and Analysis, Numerical Algorithms, Differential Equations, Compact Modeling, GPU, Power Distribution Networks, Power Delievery Networks, ASIC design
Stay tuned
Design and Design Automations in Placement, Synthesis of 2D/3D-ICs (Jun. 2013 - present)
Description: Design automation algorithms to investigate the floorplanning and synthesis for 2D/3D integrated circuits. The goal is to extract and manipulate the topology of 2D/3D geometry for physical layout.
Keywords: Physical Design, Placement, ePlace, Nesterov's Method, FFT, Linear and Nonlinear Programming, Combinatorial Optimization, VLSI Design, VLSI Synthesis, Computer Architecture, Interconnect Network.
Stochastic Algorithms for VLSI chip parasitic extraction field solver (Feb. 2011 - Jul. 2012)
Description: To extract capacitance parameters in VLSI design by devising floating random walk algorithms. This method improves scalability and efficiency for large-scale numerical problems. Some pratical software packages have been prototyped, which can be found in Sec. Software on this page. [link]
Keywords: Floating Random Walk Algorithms, Multi-thread Programming, GPU, 3D Space Management, Importance/Stratified Sampling, Monte Carlo Algorithm
Misc.
My education background dangles in EECS and Applied Math.
Thanks to the people around in CS/EE/Math departments and even my roommates, who bring to me the beauty of theoritical parts
of kernel solvers, numerical solvers, optimizers, machine learning as well as their applications on computer systems designs, programming.
I am a fan of C/C++, Javascript, Node.js and MATLAB, sometimes use Python, Haskell and play around with LLVM for Compiler and Computer Architecture.
“But it's the human time that in the end matters the most.” by MIT News HPC with ease
