Hao Zhuang - Computer Science and Engineering, University of California, San Diego
Computer Science & Engineering Department, University of California, San Diego, CA, USA
Address: 9500 Gilman Dr., EBU3, CSE Dept., La Jolla, CA, 92093-0404
hao.zhuang [at] cs.ucsd.edu
I am a 3rd year PhD student in Computer Science Department at University of California, San Diego,
and working with Prof. Chung-Kuan Cheng, who is an IEEE Fellow and Distinguished Professor.
In our group, we have been building numerical solvers for large-scale optimization and simulation software to help very large-scale integration designs (VLSI).
Some of my codes can handle the computational problems with billions of instances. Parts of my works are contributed to commerical products along previous development experiences.
Many of our ideas can be traced back to the areas of matrix computation, numerical analysis, (numerical) optimization, graph partitioning, statistics, computer graphics and machine learning.
Interestingly, we still frequently use at least 4 out of the top 10 algorithm in 20th century.
Currently, I have been involved in (1) developing algorithms VLSI computer-aided (CAD) software for large-scale SPICE-level circuit simulation, which
reduces the period of modern VLSI design verification cycles, and also maintain the high fidelity of solutions;
(2) I am also collaborating with my colleagues (Dr. Jingwei Lu,
now a lead software engineer at Cadence Design Systems, and Ilgweon Kang) and building optimization algorithms inside electronics design automation (EDA) software for VLSI global placement
ePlace to push modern low power, high speed VLSI designs, as well as pave the way for the future computer architecture using 3D structure; (3) Before those, I conducted research in Tsinghua University and was a main developer of RWCap,
the current leading academic CAD software for VLSI interconnect capacitance extraction based on random-walk algorithm, with Prof. Wenjian Yu.
applied algorithms and mathematics, numerical optimizations and simulation, and large-scale computing system for design automation algorithm and applications to computer hardware, also known as another kind of large-scale problem (think about the number of transistors in a mordern CPU chip as the problem size).
Since we have to deal with many aspects of CAD algorithm and software development, I have to enjoy research on differential equations and optimization problems in applied mathematics. Besides,
I also nurture the habit of being open to the challenges from distributed/parallel computing systems and large-scale numerical algorithms, as well as high performance programming language and compilers.
Some of them are still at the early stages, which I have been growing in our CS department.
Qualcomm FMA Fellowship (2014).
Charles Lee Powell Fellowship (2013).
Peking University Wusi Scholarship (2011).
Updates (2012 - present)
Feb. 2015: One paper got accepted by the top-tier EDA conference ACM/IEEE Design Automation Conference (DAC) 2015, San Francisco, CA.
Nov. 2014: (1) Our journal paper about VLSI physical design placement (ePlace) using one of accelerated gradient methods – Nesterov's optimization algorithm and FFT solver got accepted by the top-tier EDA journal IEEE Trans. CAD (TCAD); (2) Served as the computer system administrator at the VLSI design lab. I am currently the system programmer of the internal system - feynman dot ucsd dot edu.
Sep. 2014: Became 3rd year PhD student at CSE Dept., UCSD.
June 2014: (1) Attended ACM/IEEE DAC 2014, and presented the work [pdf] [slides] to simulate power grid network using matrix exponential integrators, Krylov subspace algorithms, and its distributed computation framework.
(2) Passed UCSD CSE Ph.D's research exam (Committee members: Prof. Steven Swanson (chair), Prof. Sanjoy Dasgupta, and Prof. Lawrence Saul).
(3) Started R&D software engineering intern at Synopsys, Inc.,
and to live at the campus of Stanford University at the end of month.
(4) Gave a research talk at Synopsys, Inc.
Apr. 2014: Attended UC San Diego Jacob School of Engineering's Research Expo
Feb. 2014: One paper got accepted by the top-tier ACM/IEEE Design Automation Conference (DAC) 2014, San Francisco, CA, thanks my co-authors, Dr. Shih-Hung Weng (now a research scientist with Facebook, Inc.) and J.-H. Lin, and Prof. C. K. Cheng.
Dec. 2013: Gave a talk on matrix exponential based circuit simulation in EDA Lab, Tsinghua University, hosted by Prof Wenjian Yu.
May 2013: Our lab was awarded with Qualcomm FMA Fellowship.
Sep. 2012: Joined Computer Science & Engineering Department, University of California, San Diego, CA.
Jul. 2012: Graduated from Peking University, Beijing, China, and finished the joint research work with Tsinghua University.
Feb. 2012: Awarded with Charles Lee Powell Fellowship.
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(Top-tier journals: TCAD. Top-tier and good conferences: DAC, ICCAD and DATE, ASP-DAC)
[TCAD15] Jingwei Lu, Hao Zhuang, Pengwen Chen, Hongliang Chang, Chin-Chih Chang, Yiu-Chung Wong, Lu Sha, Dennis Huang, Yufeng Luo, Chin-Chi Teng, Chung-Kuan Cheng, “ePlace-MS: Electrostatics based Placement for Mixed-Size Integrated Circuits,”, IEEE Trans. Computer-Aided Design (TCAD). Jan. 2015.[Special Issues 2015] (paper).(VLSI placement, optimization algorithm, FFT solver application)
[DAC15] Hao Zhuang, Wenjian Yu, Ilgweon Kang, Xinan Wang, Chung-Kuan Cheng, “An Algorithmic Framework of Large-Scale Circuit Simulation Using Exponential Integrators,” Proc. ACM/EDAC/IEEE Design Automation Conference (DAC), June 2015 (accepted).
(circuit simulation, digital systems, matrix exponential, Krylov subspace, large scale computing)
[EMC15] Hao Zhuang, Xinan Wang, Ilgweon Kang, Jeng-Hau Lin, Chung-Kuan Cheng, “Dynamic Analysis of Power Delivery Network with Nonlinear Components Using Matrix Exponential Method,” Proc. IEEE EMC and SI, March 2015 (accepted)
(power delivery network, power grid, circuit simulation, matrix exponential, large scale computing)
[DAC14] Hao Zhuang, Shih-Hung Weng, Jeng-Hau Lin, Chung-Kuan Cheng, “MATEX: A Distributed Framework for Transient Simulation of Power Distribution Networks,” Proc. ACM/EDAC/IEEE Design Automation Conference (DAC), June 2014. [pdf] [slides] [poster] (acceptance rate: 22.1%, 174/787) (power delivery network, distributed computing algorithm, circuit simulation, matrix exponential, large scale computing)
[TCAD13] Wenjian Yu*, Hao Zhuang, Chao Zhang, Gang Hu, and Zhi Liu, “RWCap: A floating random walk solver for 3-D capacitance extraction of VLSI interconnects,” IEEE Trans. Computer-Aided Design (TCAD), March, 2013. listed as one of the TCAD popular papers and best paper award nomination 2014
[pdf] [software package]. *- Hao Zhuang (1st student author)'s research advisor during this work
(chip interconnect, extraction and modeling, statistical algorithm, random sampling)
[SMPT13] Wenjian Yu, Kuangya Zhai, Hao Zhuang, Junqing Chen, “Accelerated floating random walk algorithm for the electrostatic computation with 3-D rectilinear-shaped conductors,” Elsevier Simulation Modelling Practice and Theory, 34(5): 20-36, 2013. [pdf]
(chip interconnect, extraction and modeling, GPU computing)
[DATE13] Kuangya Zhai, Wenjian Yu, Hao Zhuang, “GPU-Friendly floating random walk algorithm for capacitance extraction of VLSI interconnects,” in Proc. IEEE Design, Automation & Test in Europe (DATE), Mar. 2013, pp. 1661-1666. [pdf] (acceptance rate: 36%)
(chip interconnect, extraction and modeling, GPU computing)
[ICCCAS13] Hao Zhuang, Jingwei Lu, Kambiz Samadi, Yang Du and Chung-Kuan Cheng, “Performance-Driven Placement for Design of Rotation and Right Arithmetic Shifters in Monolithic 3D ICs,” Proc. IEEE ICCCAS, Oct. 2013. [pdf] [slides]
(VLSI placement, optimization algorithm, 3D-IC, low power design)
[ICCCAS13a] Haibing Su, Hao Liu, Shih-Hung Weng, Hui Wang, Aliasgar Presswala, Hao Zhuang, Jeng-Hau Lin, Patrick Mercier, Chung-Kuan Cheng, “A non-contact biopotential sensing system with motion artifact suppression,” Proc. IEEE ICCCAS, Oct. 2013.
(sensor, ECG, circuit)
[ASICON13] Hao Zhuang, Shih-Hung Weng, Chung-Kuan Cheng, “Power Grid Simulation using Matrix Exponential Method with Rational Krylov Subspaces,” Proc. IEEE Intl. Conf. on ASIC (ASICON), Oct. 2013. Updated on [arXiv] [pdf] [slides]
(power delivery network, circuit simulation, numerical algorithm)
Before 2012 (Selected)
[ASPDAC12] Hao Zhuang, Wenjian Yu, Gang Hu, Zhi Liu, Zuochang Ye, “Fast floating random walk algorithm for multi-dielectric capacitance extraction with numerical characterization of Green's functions,” in Proc. ACM/IEEE Asia & South Pacific Design Automation Conf. (ASP-DAC), Jan. 2012, pp. 377-382. [pdf] (acceptance rate: 34%, 99/288)
(chip interconnect, extraction and modeling, random algorithm, multithreaded programming)
[ASICON11] Hao Zhuang, Wenjian Yu, Gang Hu, Zuochang Ye, “Numerical characterization of multi-dielectric Green's function for floating random walk based capacitance extraction,” Proc. IEEE Intl. Conf. ASIC (ASICON), Oct. 2011, pp. 361-364. [pdf] [slides]
(chip interconnect, extraction and modeling, random algorithm, field solver)
Hao Zhuang, “FFT multiplication/convolution application,” pp. 5-7 of [pdf] for the problem 3 in [pdf].
Hao Zhuang, Jin Wang, “Sparse matrix-vector multipciation (SpMV) with MPI,” Dec. 2012 [report].
Hao Zhuang, “Hacking SPICE” [link].
Circuit Simulation Algorithms and its Parallel/Distributed Processing, Applications of Power Network Analysis (Mar. 2013 - present)
Description: “To analyze and verify VLSI systems via full circuit simulation and to demonstrate vastly improved scalability in order to raise the quality and scope of predictive circuit modeling. VLSI circuit simulation has become critical due to interconnect dominance of advanced fabrication technologies. Functional modules are integrated through substrates and connected by wires with parasitics. A simulation of the whole system will empower designers with a full grasp of the transient behavior of the circuits.”
Keywords: Matrix Exponential, Krylov Subspace, Distributed Computing, Parallel Computing, VLSI Design and Analysis,
Numerical Algorithms, Differential Equations, Compact Modeling, GPU, Power Distribution Networks, Power Delievery Networks, ASIC design.
Advisor: Prof. Chung-Kuan Cheng.
Academic collaborators: Dr. Shih-Hung Weng, Ilgweon Kang,
Prof. Wenjian Yu.
Papers: [DAC15] [DAC14] [EMC15] [ASICON13]
Design and Design Automations in Placement, Synthesis of 2D/3D-ICs (Jun. 2013 - present) [ePlace project website]
Description: Design automation algorithms to investigate the floorplanning and synthesis for 2D/3D integrated circuits. The goal is to extract and manipulate the topology of 2D/3D geometry for physical layout. We mimic the electrostatics for placement problem, and use optimization algorithms to reduce the compoiste objective functions. The placement solver also smartly adopts fast Fourier transformation (FFT) to accelerate its optimization process (The 2D placement algorithm research is supported by Cadence Design Systems). The design automation research for future computer architecture using 3D-ICs is also supported by Qualcomm FMA fellowship 2013.
Keywords: Physical Design, Placement, ePlace, Nesterov's Method, FFT, Linear and Nonlinear Programming, Combinatorial Optimization, VLSI Design, VLSI Synthesis, Computer Architecture, Interconnect Network.
Advisor: Prof. Chung-Kuan Cheng.
Academic collaborators: Dr. Jingwei Lu, Ilgweon Kang.
Papers: [TCAD15] [ICCCAS13]
Stochastic Algorithms for VLSI chip parasitic extraction field solver (Feb. 2011 - Jul. 2012) [RWCap project website] and [RWCap2 new project webiste]
Description: To extract capacitance parameters in VLSI design by devising floating random walk algorithms. This method improves scalability and efficiency for large-scale numerical problems. Some pratical software packages have been developed.
Keywords: Floating Random Walk Algorithms, Multi-thread Programming, GPU, 3D Space Management, Importance/Stratified Sampling, Monte Carlo Algorithm.
Advisor: Prof. Wenjian Yu.
Academic collaborators: Chao Zhang, Kuangya Zhai, Zhi Liu, Gang Hu, Prof. Zuochang Ye.
Papers: [TCAD13] [SMPT13] [DATE13] [ASPDAC12] [ASICON11]
Academic Software, Systems and Tools
RWCap: a multi-threaded 3-D floating random walk algorithm based capacitance solver for VLSI Parastic extraction (Implementation using C++, and POSIX pthread)
Contributors: Hao Zhuang, Chao Zhang, Gang Hu, Kuangya Zhai, Zhi Liu, Ting Dai. Supervisor: Wenjian Yu.
Contributors: Chao Zhang, Hao Zhuang. Supervisor: Wenjian Yu
Please check Prof. Wenjian Yu's page for the latest updates.
ePlace: a electrostatics based placmeent using FFT and accelerated gradient method – Nesterov's optimization algorithm.
Active developers: Jingwei Lu, Ilgweon Kang, Hao Zhuang. Supervisor: Chung-Kuan Cheng.
Active developers: Ilgweon Kang, Jingwei Lu, Hao Zhuang. Supervisor: Chung-Kuan Cheng.
MATEX: a SPICE-like circuit simulation using matrix exponential integration
It has been under in-house test.
Research and Working Expeirence
Synopsys, Inc., Mountain View, CA (R&D Technical Intern/Software Engineering Intern, 2014.06-2014.09)
Department of Computer Science and Engineering, University of California, San Diego, CA (Research Assistant, 2012.09-present)
Qualcomm Research and UCSD JSOE, San Diego, CA (FMA Student Researcher, 2013.06-2014.06)
TNList (Tsinghua National Lab for Information Science and Technology), Beijing, China (Summer Intern, 2012.04-2012.07)
EDA Lab, Department of Computer Science and Technology, Tsinghua University, Beijing, China (Research Assistant, 2011.01-2012.03)
TSRC Lab, School of EECS, Peking University, Beijing, China (Research Assistant, 2008.10-2012.07)
IEEE student memeber since 2011.
ACM student memeber since 2014.
SIAM student memeber since 2014.
External reviewer, ACM/IEEE Design Automation Conference (DAC).
External reviewer, ACM/IEEE International Symposium on Physical Design (ISPD).
Reviewer, IEEE Transaction on Computer Aided Design (TCAD).
Computer Science (CS)
CSE202: Algorithms and Data Structures (Prof. Russell Impagliazzo)
-- Project: Cache-Oblivious Algorithm and Data Structures.
-- [Solution] of final
CSE230: Programming Language (Prof. Ranjit Jhala)
-- Actually, it is a functional language course, talking about Haskell.
CSE231: Advanced Compilers (Prof. Sorin Lerner)
-- Final Project: Verilog Generation of Sub-Blocks within UCSD Conservation Cores Architecture (using LLVM, within Prof. Micheal Taylor's group) [slides].
CSE240: Principles in Computer Architecture (Prof. Dean Tullsen)
-- Project 1: Branch Predictor Design and Simulation.
-- Project 2: Cache Design and Simulation.
CSE120: Principles of Operating Systems (Prof. Joseph Pasquale)
-- Have fun with xv6@MIT and qemu by self.
CSE260: Parallel Computation (Prof. Scott Baden)
-- Final Project: Parallel Matrix Vector Multiplication using MPI [report].
-- Also learn about GPU, CUDA, OpenMP, pthread, MPI.
CSE223B: Distributed Computing and Systems (Prof. Alex Snoeren)
--Final Project (the top-ranked project in the class): Trusted Bridge - Online Distributed Synchronized Storage Systems (using C++, node.js, python), we wrote a simple online storage systems, also interacted with Dropbox API, Google Drive API for storage aggregations [report]. Afterwards, thanks to my classmates’ great efforts (excluding me), the prototype now transits to TrustedBridge product.
Electrical Engineering (EE)
My education background dangles in EECS and Applied Math.
Thanks to the people around in CS/EE/Math departments and even my roommates, who bring to me the beauty of theoritical parts
of kernel solvers, numerical solvers, optimizers, machine learning as well as their applications on computer systems designs, programming.
“But it's the human time that in the end matters the most.” by MIT News HPC with ease
Links and Useful Notes (at least to me)