Hao Zhuang, Ph.D., UCSD Computer Science
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Research Interests:
My research interests are
Computer architecture, compiler, design methodologies and automation for computing systems or accelerators of
machine learning/deep learning architectures, espcially for computer vision, video codec, video compression, and image processing;
software and hardware co-design, AI accelerators;
VLSI chip design and automation for data centers and mobile devices;
Matrix and numerical computing, parallel computing, and high-performance computing (HPC);
EDA, VLSI CAD, VLSI Design, semiconductors.
Services
Topic Program Committee (TPC) of ACM/IEEE Design Automation Conference (DAC), 2019.
Reviewer of
Journals - IEEE Transaction on Computer Aided Design (TCAD), Integration, the Journal of VLSI, ACM Design Automation of Electronic Systems (TODAES), IET Cyber-Physical Systems: Theory & Applications, IEEE Trans. Magnetics - Conferences
Conferences: ACM/IEEE Design Automation Conference (DAC), Very Large Scale Integration and Systems-on-Chip (VLSI-SoC), ACM/IEEE International Symposium on Physical Design (ISPD), ACM/IEEE International Conference on Computer Aided Design (ICCAD).
Graduate Schools:
I got my Ph.D. degree in Computer Science from University of California, San Deigo, CA, USA (UCSD) in 2016 (depth course track - Computer Systems). My graduate research projects included
Numerical algorithms, matrix computation, ordinary differential equantion (ODE) solvers, and stochastic solvers with the applications in
The analysis of large-scale nonlinear/linear dynamical systems via exponenital integration. [DAC’15]/[IEEE CASM’16]
Fast power grid network simulation via exponenital integrators and its distributed computing paradigm. [DAC’14]
Floating random walk algorithms, Monte Carlo sampling, and parallel programing for VLSI network extraction. [IEEE TCAD’13]
Physical design in design automation and computer-aided design (EDA/CAD) for building computers and chips. [IEEE TCAD’15]
Datapath synthesis, computer architecture, low power design, 3D-ICs (with Qualcomm Research). [ICCCAS’13]
Embedded real-time systems and parallel programming language (with UCSD MESL group). [ACM SIGBED Review’17]
My PhD research was funded by Charles Lee Powell Foundation and Qualcomm FMA program. Some of the techniques I developed with my colleagues during both my master and PhD research had been commercialized or purchased into the industry.
I am a regular donator to UCSF Cancer research, UCSD research, and Wikimedia. I encourage people to support the medical development and the distribution of public knowledge. I believe the technologies play the essential role for the education and society, I am also a user of MIT OpenCourseWare. During the spare time of my PhD study, I helped several projects related to online collaboration and personalized e-learning systems to make education massive and accessible to the world. I have worked with linguists, teachers, and professors, used techniques from natural language processing, computational linguistics, and distributed systems.
I got married to Xiao Liu, who can jump way farther than me. She was a national college track and field athlete, and represented China and Peking University for International 2007, 2009 (final 8th place), 2011 Summer Universiade. I am a fan of NBA and play basketball games weekly, usually as position 2 on the court.
Selected Publications [Full List] [Google Scholar Citations]
Fast Floating Random Walk Algorithm For Multi-dielectric Capacitance Extraction with Numerical Characterization of Green's Functions
Hao Zhuang, Wenjian Yu, Gang Hu, Zhi Liu, and Zuochang Ye
ACM/IEEE Asia & South Pacific Design Automation Conference (ASP-DAC), 2012
- Download [software package]
RWCap: A Floating Random Walk Solver for 3-D Capacitance Extraction of VLSI Interconnects
Wenjian Yu, Hao Zhuang, Chao Zhang, Gang Hu, and Zhi Liu,
IEEE Transactions on Computer-Aided Design (TCAD), March, 2013.
- Nominated for TCAD's Donald O. Peterson Best Paper Award 2014 & Listed as one of TCAD popular papers.
- RWCap Homepage
MATEX: A Distributed Framework for Transient Simulation of Power Distribution Networks
Hao Zhuang, Shih-Hung Weng, Jeng-Hau Lin, and Chung-Kuan Cheng
ACM/IEEE Design Automation Conference (DAC), June 2014.
Simulation Algorithms with Exponential Integration for Time-Domain Analysis of Large-Scale Power Delivery Networks.
Hao Zhuang, Wenjian Yu, Shih-Hung Weng, Ilgweon Kang, Jeng-Hau Lin, Xiang Zhang, Ryan Coutts, and Chung-Kuan Cheng.
IEEE Transactions on Computer-Aided Design (TCAD) 2016 [IEEEXplore]
- The journal version of MATEX.
From Circuit Theory, Simulation to SPICE_Diego: A Matrix Exponential Approach for Time Domain Analysis of Large Scale Circuits. [update]
Hao Zhuang, Xinyuan Wang, Quan Chen, Pengwen Chen, and Chung-Kuan Cheng.
IEEE Circuits and Systems Magazine 2016
- Dedicated to the memory of Prof. Ernest S. Kuh, UC Berkeley.
An Algorithmic Framework of Large-Scale Circuit Simulation Using Exponential Integrators
Hao Zhuang, Wenjian Yu, Ilgweon Kang, Xinan Wang, and Chung-Kuan Cheng
ACM/IEEE Design Automation Conference (DAC), June 2015
Selected Software Packages [Full List]
RWCap: a multi-threaded 3-D floating random walk algorithm based capacitance extraction software (C++) for VLSI interconnect networks. Please check Prof. Wenjian Yu's page for the latest updates.
Selected Patent [Full List]
Wenjian Yu and Hao Zhuang, “Method for extracting and calculating capacitance parameter based on random walk in integrated circuit design,” Dec 11, 2013, Publication number: CN102651047 B
Memberships
IEEE student memeber 2011-2016; ACM student memeber and SIAM student memeber 2014-2016.
Honors
Qualcomm FMA Fellowship (2013-2014): one of the four recipients [award].
Charles Lee Powell Fellowship (2012-2015): for supporting outstanding PhD engineering students.
Peking University Wu-Si Scholarship (2011).
Academic Experience [Details]
Department of Computer Science and Engineering, University of California, San Diego, CA, USA (Teaching Assistant, 2014.10-2014.12)
Department of Computer Science and Engineering, University of California, San Diego, CA, USA (Research Assistant, 2012.09-2015.06)
EDA Lab, Department of Computer Science and Technology, Tsinghua University, Beijing, China (Research Assistant, 2011.01-2012.03)
TSRC Lab, School of EECS, Peking University, Beijing, China (Research Assistant, 2008.10-2012.07)
TNList (Tsinghua National Lab for Information Science and Technology), Beijing, China (Research Intern, 2012.04-2012.07)
Selected Talks [Full List]
“Matrix Exponential Integration in Time-domain Analysis of Circuit Simulation,” at ECE Department, Peking University, China, Oct 2015 [Flyer]
“Matrix Exponential Integration in Time-Domain Analysis of Circuit Simulation,” at Department of Electrical and Electronics Engineering, The University of Hong Kong, Hong Kong, Oct. 2015
“Algorithms for Dynamic Power Grid Simulation Using Matrix Exponentials,” at ANSYS, Inc., San Jose, Sept. 2015.
Teaching
Assistant, CSE245: Numerical Algorithms and Circuit Simulation (2015 Winter)
Teaching Assistant, CSE140: Components and Design Techniques for Digital Systems (2014 Autumn)
-- Textbook: Digital Design and Computer Architecture (2nd Edition) by David Mooney Harris and Sarah L. Harris
Industry [Details]
2018.07-: Google, Mountain View, CA (Software Engineer)
2015.06-2018.07: ANSYS, Inc., San Jose, CA (Senior Software Developer)
2014.06-2014.09: Synopsys, Inc., Mountain View, CA, USA (Software Engineering Intern)
2013.06-2014.06: Qualcomm Research & UCSD JSOE, San Diego, CA, USA (FMA Ph.D. Research Fellow)
Some Snapshots
[Google] I am a Software Engineer at Google, Mountain View, CA, working on software, computer architecture, chips and hardware research for mobile, data centers, and AI/Deep Learning/Computer Vision applications.
[ANSYS, Apache] Before Google, I was a Senior Software Developer at ANSYS Semiconductor Business Unit (formerly Apache Design Solutions Inc, a startup acquired by ANSYS) for 3 years since 2015. I worked on Design Automation (EDA/VLSI CAD) research using numerical algorithms, machine Learning, and distributed computing for circuit-level, gate/RTL-level simulation to provide the industrial standard ASIC, VLSI chip power sign-off software. The products have been used over a decade for taping out CPU, GPU, and AI chips. My role was to lead and architect the machine learning-assisted products (for chip timing, dynamic voltage drops, power/EM, and RTL optimizations) in Semiconductor Business Unit on top of the big data distributed system product.
For simulation solver in the flagship product ANSYS RedHawk, I mainly worked with Senior Software Architect Dr. Steven P. McCormick (MIT EECS PhD’89), who was one of pioneers in VLSI model order reduction research.
To solve challenging machine learning problems in design automation, I worked with Chief Technologiest and Apache co-founder Dr. Norman Chang (UC Berkeley EECS PhD’90). We worked with Nvidia chip design team and Prof. Jang's machine learning lab at National Taiwan University.
I also worked on the parasitic extraction, circuit graph network reductions, model order reduction Chip Power Model integration in the latest production line for Automotive, Mobile and HPC Electronic Designs.
It was my privilege to work with the teams consist of legends in the area of design automation research, such as the researcher of AWE, the creators of MIT FastCap, CMU PRIMA, UT RICE, Synopsys PrimeTime, and Apache Redhawk.
[Synopsys] I wroted software at Synopsys Inc as a Summer Intern in 2014, working on graph partitioning algorithm and its multi-threaded programs. The algorithm I help developed in that summer scaled up the matrix solver for full-chip power network analysis with over billion graph nodes.
[Qualcomm Research] While my PhD research, I was also with Qualcomm Research as one of FMA fellows and worked on low-power datapath synthesis, computer architecture, and 3D-ICs.
