Hao Zhuang - Computer Science and Engineering, University of California, San Diego

3rd Ph.D. student in Computer Science & Computer Engineering @ 2015. a.k.a Howard, (why? Someone: How (Hao,) can I do this? Me: Yes. Someone: …)
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Computer Science & Engineering Department, University of California, San Diego, CA, USA
Mailing: 9500 Gilman Dr., EBU3, CSE Dept., La Jolla, CA, 92093-0404
E-mail: hao.zhuang [at] cs.ucsd.edu

External Acadmeic Profiles: Google Scholar, DBLP,
Code hub (there are hidden projects): me@github, me@bitbucket;
Misc: me@wordpress topcoder codeforces

View Hao Zhuang's profile on LinkedIn

We have been building numerical solvers for large-scale optimization and simulation software to help very large-scale integration designs. Many ideas are borrowed from the areas of matrix computation, optimization and machine learning. Interestingly, we still frequently use at least 4 out of the top 10 algorithm in 20th century.

Current Research Interests:

numerical algorithms, numerical optimizations, nonlinear optimization, nonlinear simulation, circuit simulation, learning, and large-scale computing system for design automation algorithm and applications to computer hardware, also known as another kind of solving large-scale problem (think about the number of transistors in a chip as the problem size). I am also opened to the challenges from distributed computing systems and large-scale numerical algorithms, as well as high performance programming language and compiler (early stage). I enjoy research on differential equations and optimization problems in applied mathematics.


  • Feb. 2015: One paper got accepted by the top-tier EDA conference ACM/IEEE Design Automation Conference (DAC) 2015, San Francisco, CA.

  • Nov. 2014: (1) Our journal paper about VLSI physical design placement (ePlace) using one of accelerated gradient methods – Nesterov's optimization algorithm and FFT solver got accepted by the top-tier EDA journal IEEE Trans. CAD (TCAD); (2) Served as the computer system administrator at the VLSI design lab. I am currently the system programmer of the internal system - feynman dot ucsd dot edu.

  • Sep. 2014: Became 3rd year PhD student at CSE Dept., UCSD.

  • June 2014: (1) Attended ACM/IEEE DAC 2014, and presented the work [pdf] [slides] to simulate power grid network using matrix exponential integrators, Krylov subspace algorithms, and its distributed computation framework. (2) Passed UCSD CSE Ph.D's research exam (Committee members: Prof. Steven Swanson (chair), Prof. Sanjoy Dasgupta, and Prof. Lawrence Saul). (3) Started R&D software engineering intern at Synopsys, Inc., and to live at the campus of Stanford University at the end of month. (4) Gave a research talk at Synopsys, Inc.

  • Apr. 2014: Attended UC San Diego Jacob School of Engineering's Research Expo

  • Feb. 2014: One paper got accepted by the top-tier ACM/IEEE Design Automation Conference (DAC) 2014, San Francisco, CA, thanks my co-authors, Dr. S.-H. Weng (now a research scientist with Facebook, Inc.) and J.-H. Lin, and Prof. C. K. Cheng.

  • Dec. 2013: Gave a talk on matrix exponential based circuit simulation in EDA Lab, Tsinghua University, hosted by Prof Wenjian Yu.

  • May 2013: Our lab was awarded with Qualcomm FMA Fellowship.

  • Sep. 2012: Joined Computer Science & Engineering Department, University of California, San Diego, CA.

  • Jul. 2012: Graduated from Peking University, Beijing, China, and finished the joint research work with Tsinghua University.

  • Feb. 2012: Awarded with Charles Lee Powell Fellowship.


Please note that papers linked here represent author preprints or updated drafts. The official, published version must be obtained from the publisher's website or the published print copy. This material is presented here to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each document's copyright terms. In most cases, these works may not be reposted without the explicit permission of the copyright holder. Permission is given to make digital or hard copies of all or part of this material without fee for personal or classroom use, provided that the copies are not made or distributed for profit or commercial advantage, and that copies bear the appropriate copyright notice and the full bibliographic citation on the first page. Copyrights for components of this work owned by others must also be honored. To copy otherwise, to republish, to post on servers, to redistribute to lists, etc. requires specific permission and/or a fee. In particular, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works, must be obtained from the copyright owner. Please note further that any opinions, findings, conclusions, or recommendations expressed in this material are those of the authors and do not necessarily reflect the views of the sponsoring agencies, employers, or publishers.


(Top-tier and good conferences: DAC, ICCAD and DATE, ASP-DAC)


  • [DAC15] Hao Zhuang, Wenjian Yu, Ilgweon Kang, Xinan Wang, Chung-Kuan Cheng, “An Algorithmic Framework of Large-Scale Circuit Simulation Using Exponential Integrators,” Proc. ACM/EDAC/IEEE Design Automation Conference (DAC), June 2015 (accepted). (circuit simulation, digital systems, matrix exponential, Krylov subspace, large scale computing)

  • [EMC15] Hao Zhuang, Xinan Wang, Ilgweon Kang, Jeng-Hau Lin, Chung-Kuan Cheng, “Dynamic Analysis of Power Delivery Network with Nonlinear Components Using Matrix Exponential Method,” Proc. IEEE EMC and SI, March 2015 (accepted) (power delivery network, power grid, circuit simulation, matrix exponential, large scale computing)


  • [DAC14] Hao Zhuang, Shih-Hung Weng, Jeng-Hau Lin, Chung-Kuan Cheng, “MATEX: A Distributed Framework for Transient Simulation of Power Distribution Networks,” Proc. ACM/EDAC/IEEE Design Automation Conference (DAC), June 2014. [pdf] [slides] [poster] (acceptance rate: 22.1%, 174/787) (power delivery network, distributed computing algorithm, circuit simulation, matrix exponential, large scale computing)


  • [ICCCAS13] Hao Zhuang, Jingwei Lu, Kambiz Samadi, Yang Du and Chung-Kuan Cheng, “Performance-Driven Placement for Design of Rotation and Right Arithmetic Shifters in Monolithic 3D ICs,” Proc. IEEE ICCCAS, Oct. 2013. [pdf] [slides] (VLSI placement, optimization algorithm, 3D-IC, low power design)

  • [ICCCAS13a] Haibing Su, Hao Liu, Shih-Hung Weng, Hui Wang, Aliasgar Presswala, Hao Zhuang, Jeng-Hau Lin, Patrick Mercier, Chung-Kuan Cheng, “A non-contact biopotential sensing system with motion artifact suppression,” Proc. IEEE ICCCAS, Oct. 2013. (sensor, ECG, circuit)

  • [ASICON13] Hao Zhuang, Shih-Hung Weng, Chung-Kuan Cheng, “Power Grid Simulation using Matrix Exponential Method with Rational Krylov Subspaces,” Proc. IEEE Intl. Conf. on ASIC (ASICON), Oct. 2013. Updated on [arXiv] [pdf] [slides] (power delivery network, circuit simulation, numerical algorithm)

  • [DATE13] Kuangya Zhai, Wenjian Yu, Hao Zhuang, “GPU-Friendly floating random walk algorithm for capacitance extraction of VLSI interconnects,” in Proc. IEEE Design, Automation & Test in Europe (DATE), Mar. 2013, pp. 1661-1666. [pdf] (acceptance rate: 36%) (chip interconnect, extraction and modeling, GPU computing)


  • [ASPDAC12] Hao Zhuang, Wenjian Yu, Gang Hu, Zhi Liu, Zuochang Ye, “Fast floating random walk algorithm for multi-dielectric capacitance extraction with numerical characterization of Green's functions,” in Proc. ACM/IEEE Asia & South Pacific Design Automation Conf. (ASP-DAC), Jan. 2012, pp. 377-382. [pdf] (acceptance rate: 34%, 99/288) (chip interconnect, extraction and modeling, random algorithm, multithreaded programming)


  • [ASICON11] Hao Zhuang, Wenjian Yu, Gang Hu, Zuochang Ye, “Numerical characterization of multi-dielectric Green's function for floating random walk based capacitance extraction,” Proc. IEEE Intl. Conf. ASIC (ASICON), Oct. 2011, pp. 361-364. [pdf] [slides] (chip interconnect, extraction and modeling, random algorithm, field solver)


(Top-tier journals: TCAD)


  • [TCAD15] Jingwei Lu, Hao Zhuang, Pengwen Chen, Hongliang Chang, Chin-Chih Chang, Yiu-Chung Wong, Lu Sha, Dennis Huang, Yufeng Luo, Chin-Chi Teng, Chung-Kuan Cheng, “ePlace-MS: Electrostatics based Placement for Mixed-Size Integrated Circuits,”, IEEE Trans. Computer-Aided Design (TCAD). Jan. 2015.[Special Issues 2015] (paper).(VLSI placement, optimization algorithm, FFT solver application)


  • [TCAD13] Wenjian Yu*, Hao Zhuang, Chao Zhang, Gang Hu, and Zhi Liu, “RWCap: A floating random walk solver for 3-D capacitance extraction of VLSI interconnects,” IEEE Trans. Computer-Aided Design (TCAD), March, 2013. listed as one of the TCAD popular papers and best paper award nomination 2014 [pdf] [software package]. *- Hao Zhuang (1st student author)'s research advisor during this work (chip interconnect, extraction and modeling, statistical algorithm, random sampling)

  • [SMPT13] Wenjian Yu, Kuangya Zhai, Hao Zhuang, Junqing Chen, “Accelerated floating random walk algorithm for the electrostatic computation with 3-D rectilinear-shaped conductors,” Elsevier Simulation Modelling Practice and Theory, 34(5): 20-36, 2013. [pdf] (chip interconnect, extraction and modeling, GPU computing)

Other Technical Notes


  • Hao Zhuang, “FFT multiplication/convolution application,” pp. 5-7 of [pdf] for the problem 3 in [pdf].


  • Hao Zhuang, Jin Wang, “Sparse matrix-vector multipciation (SpMV) with MPI,” Dec. 2012 [report].

Research Projects

  • Circuit Simulation Algorithms and its Parallel/Distributed Processing, Applications of Power Network Analysis (Mar. 2013 - present)
    Description: “To analyze and verify VLSI systems via full circuit simulation and to demonstrate vastly improved scalability in order to raise the quality and scope of predictive circuit modeling. VLSI circuit simulation has become critical due to interconnect dominance of advanced fabrication technologies. Functional modules are integrated through substrates and connected by wires with parasitics. A simulation of the whole system will empower designers with a full grasp of the transient behavior of the circuits.” Keywords: Matrix Exponential, Krylov Subspace, Distributed Computing, Parallel Computing, VLSI Design and Analysis, Numerical Algorithms, Differential Equations, Compact Modeling, GPU, Power Distribution Networks, Power Delievery Networks, ASIC design.
    Papers: [DAC15] [DAC14] [EMC15] [ASICON13]
    Stay tuned

  • Design and Design Automations in Placement, Synthesis of 2D/3D-ICs (Jun. 2013 - present) [ePlace project website]
    Description: Design automation algorithms to investigate the floorplanning and synthesis for 2D/3D integrated circuits. The goal is to extract and manipulate the topology of 2D/3D geometry for physical layout. We mimic the electrostatics for placement problem, and use optimization algorithms to reduce the compoiste objective functions. The placement solver also smartly adopts fast Fourier transformation (FFT) to accelerate its optimization process (The 2D placement algorithm research is supported by Cadence System Design). The design automation research for future computer architecture using 3D-ICs is also supported by Qualcomm FMA fellowship 2013. Keywords: Physical Design, Placement, ePlace, Nesterov's Method, FFT, Linear and Nonlinear Programming, Combinatorial Optimization, VLSI Design, VLSI Synthesis, Computer Architecture, Interconnect Network.
    Papers: [TCAD15] [ICCCAS13]

  • Stochastic Algorithms for VLSI chip parasitic extraction field solver (Feb. 2011 - Jul. 2012) [RWCap project website] and [RWCap2 new project webiste]
    Description: To extract capacitance parameters in VLSI design by devising floating random walk algorithms. This method improves scalability and efficiency for large-scale numerical problems. Some pratical software packages have been developed. Keywords: Floating Random Walk Algorithms, Multi-thread Programming, GPU, 3D Space Management, Importance/Stratified Sampling, Monte Carlo Algorithm.
    Papers: [TCAD13] [SMPT13] [DATE13] [ASPDAC12] [ASICON11]


  1. RWCap: a multi-threaded 3-D floating random walk algorithm based capacitance solver for VLSI Parastic extraction (Implementation using C++, and POSIX pthread) Related Express

    1. RWCap (v1)
      Contributors: Hao Zhuang, Chao Zhang, Gang Hu, Kuangya Zhai, Zhi Liu, Ting Dai. Supervisor: Wenjian Yu.

    2. RWCap (v2)
      Contributors: Chao Zhang, Hao Zhuang. Supervisor: Wenjian Yu
      Please check Prof. Wenjian Yu's page for the latest updates.

  2. ePlace: a electrostatics based placmeent using FFT and accelerated gradient method – Nesterov's optimization algorithm.

    1. 2D Placement
      Active developers: Jingwei Lu, Ilgweon Kang, Hao Zhuang. Supervisor: Chung-Kuan Cheng.

    2. 3D Placement
      Active developers: Ilgweon Kang, Jingwei Lu, Hao Zhuang. Supervisor: Chung-Kuan Cheng.

  3. MATEX: a SPICE-like circuit simulation using matrix exponential integration

    1. It has been under in-house test.


Research and Working Expeirence


  • IEEE student memeber since 2011.

  • ACM student memeber since 2014.

  • SIAM student memeber since 2014.

  • External reviewer, ACM/IEEE Design Automation Conference (DAC).

  • External reviewer, ACM/IEEE International Symposium on Physical Design (ISPD).

  • Reviewer, IEEE Transaction on Computer Aided Design (TCAD).


Selected Honors

  • Qualcomm FMA Fellowship (2014).

  • Charles Lee Powell Fellowship (2013, 2015).

  • Peking University Wusi Scholarship (2011).

Selected Courses

Computer Science (CS)


Electrical Engineering (EE)


My education background dangles in EECS and Applied Math. Thanks to the people around in CS/EE/Math departments and even my roommates, who bring to me the beauty of theoritical parts of kernel solvers, numerical solvers, optimizers, machine learning as well as their applications on computer systems designs, programming.
I am a fan of C/C++, Javascript, Node.js and MATLAB, sometimes use Python, Haskell and play around with LLVM for Compiler and Computer Architecture.

“But it's the human time that in the end matters the most.” by MIT News HPC with ease

Links and Useful Notes (at least to me)

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