Hao Zhuang, Ph.D. student in Computer Science + Computer Engineering.

a.k.a Howard, (why? Someone: How (Hao,) can I do this? Me: Yes. Someone: …)
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Computer Science & Engineering Department,
University of California, San Diego, CA, USA
Mailing: 9500 Gilman Dr., EBU3, CSE Dept., La Jolla, CA, 92093-0404
E-mail: zhuangh [at] ucsd.edu
External Acadmeic Profiles: Google Scholar, DBLP;

View Hao Zhuang's profile on LinkedIn
Code repos (there are hidden projects): me@github, me@bitbucket; Misc: me@wordpress

Recent Highlights/Publications

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(Top-tier and good conferences: DAC, ICCAD and DATE, ASP-DAC)

  1. (power delivery network, distributed computing algorithm, circuit simulation, matrix exponential, large scale computing) Hao Zhuang, Shih-Hung Weng, Jeng-Hau Lin, Chung-Kuan Cheng, “MATEX: A Distributed Framework for Transient Simulation of Power Distribution Networks,” Proc. ACM/EDAC/IEEE Design Automation Conference (DAC), June 2014. [pdf] [slides] [poster] (acceptance rate: 22.1%, 174/787)

  2. (chip interconnect, extraction and modeling, random algorithm, multithreaded programming) Hao Zhuang, Wenjian Yu, Gang Hu, Zhi Liu, Zuochang Ye, “Fast floating random walk algorithm for multi-dielectric capacitance extraction with numerical characterization of Green's functions,” in Proc. ACM/IEEE Asia & South Pacific Design Automation Conf. (ASP-DAC), Jan. 2012, pp. 377-382. [pdf] (acceptance rate: 34%, 99/288)

  3. (chip interconnect, extraction and modeling, GPU computing) Kuangya Zhai, Wenjian Yu, Hao Zhuang, “GPU-Friendly floating random walk algorithm for capacitance extraction of VLSI interconnects,” in Proc. IEEE Design, Automation & Test in Europe (DATE), Mar. 2013, pp. 1661-1666. [pdf] (acceptance rate: 36%)

  4. (power delivery network, circuit simulation, numerical algorithm) Hao Zhuang, Shih-Hung Weng, Chung-Kuan Cheng, “Power Grid Simulation using Matrix Exponential Method with Rational Krylov Subspaces,” Proc. IEEE Intl. Conf. on ASIC (ASICON), 2013. Updated on [arXiv] [pdf] [slides]

  5. (chip interconnect, extraction and modeling, random algorithm, field solver) Hao Zhuang, Wenjian Yu, Gang Hu, Zuochang Ye, “Numerical characterization of multi-dielectric Green's function for floating random walk based capacitance extraction,” Proc. IEEE Intl. Conf. ASIC (ASICON), Oct. 2011, pp. 361-364. [pdf] [slides]

  6. (VLSI placement, optimization algorithm, 3D-IC, low power design) Hao Zhuang, Jingwei Lu, Kambiz Samadi, Yang Du and Chung-Kuan Cheng, “Performance-Driven Placement for Design of Rotation and Right Arithmetic Shifters in Monolithic 3D ICs,” Proc. IEEE ICCCAS, 2013. [pdf] [slides]


(Top-tier journals: TCAD)

  1. (chip interconnect, extraction and modeling, statistical algorithm, random sampling) Wenjian Yu*, Hao Zhuang, Chao Zhang, Gang Hu, and Zhi Liu, “RWCap: A floating random walk solver for 3-D capacitance extraction of VLSI interconnects,” IEEE Trans. Computer-Aided Design (TCAD), 32(3): 353-366, 2013. listed as one of the TCAD popular papers and best paper award nomination 2014 [pdf] [software package]. *- Hao Zhuang (1st student author)'s research advisor during this work

  2. (VLSI placement, optimization algorithm, FFT solver application) Jingwei Lu, Hao Zhuang, Pengwen Chen, Hongliang Chang, Chin-Chih Chang, Yiu-Chung Wong, Lu Sha, Dennis Huang, Yufeng Luo, Chin-Chi Teng, Chung-Kuan Cheng, “ePlace-MS: Electrostatics based Placement for Mixed-Size Integrated Circuits,”, IEEE Trans. Computer-Aided Design (TCAD) [Special Issues 2014] (to appear).

  3. (chip interconnect, extraction and modeling, GPU computing) Wenjian Yu, Kuangya Zhai, Hao Zhuang, Junqing Chen, “Accelerated floating random walk algorithm for the electrostatic computation with 3-D rectilinear-shaped conductors,” Elsevier Simulation Modelling Practice and Theory, 34(5): 20-36, 2013. [pdf]


Recent Software

  1. RWCap: a multi-threaded 3-D floating random walk algorithm based capacitance solver for VLSI Parastic extraction (Implementation using C++, and POSIX pthread) Related Express

    1. RWCap (v1)
      Contributors: Hao Zhuang, Chao Zhang, Gang Hu, Kuangya Zhai, Zhi Liu, Ting Dai. Supervisor: Wenjian Yu.

    2. RWCap (v2)
      Contributors: Chao Zhang, Hao Zhuang. Supervisor: Wenjian Yu
      Please check Prof. Wenjian Yu's page for the latest updates.

Research Interests

  • Algorithms, mathematical models in circuit simulation, timing and power (delivery network) analysis, placement.

  • Design automation for digital systems, VLSI chip designs and computer architecture.

  • Building high/heterogeneous performance computing algorithms and systems for VLSI CAD as well as lower power computing computer architecture.

  • Matrix computations and statistical, random algorithmms, graph algorithms for scientific simulation, data, network analysis.

  • Computer system designs.

design automation for digital systems, circuits, VLSI CAD, low-power systems and energy-efficient computer architecture, design automation and verification algorithms, numerical methods, matrix exponential operator, power/timing verification and simulation, high performance computing, scalable distributed/parallel programming, software design, data structure

Some updates

  • Nov. 2014: (1) Our placement journal paper (ePlace) to IEEE TCAD got accepted; (2) Served as the computer system administrator at the VLSI design lab.

  • June 2014: (1) Attended ACM/IEEE DAC 2014, and gave a talk. (2) Passed UCSD CSE Ph.D's research exam (Committee members: Prof. Steven Swanson (chair), Prof. Sanjoy Dasgupta, and Prof. Lawrence Saul). (3) Started R&D technical internship at Synopsys, Inc., and to live at the campus of Stanford University at the end of month. (4) Gave a research talk at Synopsys, Inc.

  • Apr. 2014: Attend UC San Diego Jacob School of Engineering's Research Expo

  • Feb. 2014: One paper got accepted by the top-tier ACM/IEEE Design Automation Conference (DAC) 2014, San Francisco, CA, thanks my co-authors, Dr. S.-H. Weng (now a research scientist with Facebook, Inc.) and J.-H. Lin, and Prof. C. K. Cheng.

  • Dec. 2013: Gave a talk on matrix exponential based circuit simulation in EDA Lab, Tsinghua University, hosted by Prof Wenjian Yu.

  • May 2013: Our lab was awarded with Qualcomm FMA Fellowship.

  • Sep. 2012: Joined Computer Science & Engineering Department, University of California, San Diego, CA.

  • Jul. 2012: Graduated from Peking University, Beijing, China, and finished the joint research work with Tsinghua University.

  • Feb. 2012: Awarded with Charles Lee Powell Fellowship.

Research and Working Expeirence


  • IEEE student memeber since 2011.

  • ACM student memeber since 2014.

  • SIAM student memeber since 2014.

  • External reviewer, ACM/IEEE Design Automation Conference (DAC).

  • External reviewer, ACM/IEEE International Symposium on Physical Design (ISPD).

  • Reviewer, IEEE Transaction on Computer Aided Design (TCAD).


Selected Courses

Computer Science (CS)


Electrical Engineering (EE)

Research Projects

  • Circuit Simulation Algorithms and its Parallel/Distributed Processing, Applications of Power Network Analysis (Mar. 2013 - present)
    Description: “To analyze and verify VLSI systems via full circuit simulation and to demonstrate vastly improved scalability in order to raise the quality and scope of predictive circuit modeling. VLSI circuit simulation has become critical due to interconnect dominance of advanced fabrication technologies. Functional modules are integrated through substrates and connected by wires with parasitics. A simulation of the whole system will empower designers with a full grasp of the transient behavior of the circuits.” [link]
    Keywords: Matrix Exponential, Krylov Subspace, Distributed Computing, Paralel Computing, VLSI Design and Analysis, Numerical Algorithms, Differential Equations, Compact Modeling, GPU, Power Distribution Networks, Power Delievery Networks, ASIC design
    Stay tuned

  • Design and Design Automations in Placement, Synthesis of 2D/3D-ICs (Jun. 2013 - present)
    Description: Design automation algorithms to investigate the floorplanning and synthesis for 2D/3D integrated circuits. The goal is to extract and manipulate the topology of 2D/3D geometry for physical layout.
    Keywords: Physical Design, Placement, ePlace, Nesterov's Method, FFT, Linear and Nonlinear Programming, Combinatorial Optimization, VLSI Design, VLSI Synthesis, Computer Architecture, Interconnect Network.

  • Stochastic Algorithms for VLSI chip parasitic extraction field solver (Feb. 2011 - Jul. 2012)
    Description: To extract capacitance parameters in VLSI design by devising floating random walk algorithms. This method improves scalability and efficiency for large-scale numerical problems. Some pratical software packages have been prototyped, which can be found in Sec. Software on this page. [link]
    Keywords: Floating Random Walk Algorithms, Multi-thread Programming, GPU, 3D Space Management, Importance/Stratified Sampling, Monte Carlo Algorithm


My education background dangles in EECS and Applied Math. Thanks to the people around in CS/EE/Math departments and even my roommates, who bring to me the beauty of theoritical parts of kernel solvers, numerical solvers, optimizers, machine learning as well as their applications on computer systems designs, programming.
I am a fan of C/C++, Javascript, Node.js and MATLAB, sometimes use Python, Haskell and play around with LLVM for Compiler and Computer Architecture.

“But it's the human time that in the end matters the most.” by MIT News HPC with ease

Links and Useful Notes (at least to me)

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