Hao Zhuang - PhD candidate in Computer Science, University of California, San Diego

a.k.a Howard
alt text 

Computer Science & Engineering Department, University of California, San Diego, CA, USA
Address: 9500 Gilman Dr., EBU3B, CSE Dept., UC San Diego, La Jolla, CA, 92093-0404
hao.zhuang [at] cs.ucsd.edu
google scholar, dblp, me@github, me@wordpress.

view hao zhuang's profile on linkedin

About: Since '12~'13 academic year, I have been a Computer Science PhD student (PhD candidate'15, degree expected '15~'16 academic year) at UC San Diego, and working with Prof. Chung-Kuan Cheng (PhD UC Berkeley EECS '84), who is an IEEE Fellow and Distinguished Professor. My major research focus is numerical and optimization algorithms as well as large-scale computing system/platform research, with the applications in design automation, very large-scale integration systems, EDA, VLSI CAD, high-dimensional (large-scale) data analysis, signal processing and semiconductor, chip/hardware designs.

In our group, we have been building numerical solvers for large-scale optimization and simulation software to help very large-scale integration designs (VLSI). Some of my codes can handle the computational problems with billions of instances. Parts of my works are contributed to commercial products along previous development experiences. I started my research on VLSI CAD/EDA after the spring festival of 2011. Many of the ideas can be traced back to the areas of matrix computation, numerical analysis, (numerical) optimization, graph partitioning, statistics, computer graphics, PageRank, machine learning, etc. We still frequently use at least 4 out of the top 10 algorithm in 20th century.

I have a broad range of interests in computer science and the applications. Currently, I have been involved in following projects:

  • Developing algorithms and VLSI computer-aided (CAD) software for next-generation large-scale SPICE-level circuit simulation. It is the key component for designs of VLSI systems, even up to computer architecture, because many derivatives depend on it, such as timing analysis, post-layout simulation, power sign-off, worst-case, Monte-Carlo simulation, and etc. We are building fast computer programs to reduce the periods of modern VLSI design verification cycles, and also maintains the high fidelity of solutions;

  • Developing parallel and distributed matrix computation algorithms for advanced large-scale dynamic power network simulation and made contributions to the leading commercial EDA products.

  • Building optimization algorithms inside electronics design automation (EDA) software for VLSI global placement ePlace to push modern low power, high speed VLSI designs, as well as pave the way for the future computer architecture using 3D structure. Collaborating with my colleagues (Dr. Jingwei Lu, now a lead software engineer at Cadence Design Systems, and Ilgweon Kang).

  • Building and improving multi-core system real-time scheduling algorithms, concurrent data structures as well as Go programming language. We want the system to be real-time computing platform for signal processing, machine learning and computer vision research. Collaborating with Zhou Fang.

Before UCSD,

  • Conducted a research project in Tsinghua University and was a main developer of RWCap (the current version), the current leading academic CAD software for VLSI interconnect capacitance extraction based on random-walk algorithm, with Prof. Wenjian Yu.

  • Conducted research on model order reduction algorithms for circuit simulation in the school of EECS, Peking University.

Research Interests: applied algorithms and mathematics, numerical optimizations and simulation, and large-scale computing system for design automation algorithm and applications to computer hardware, also known as another kind of large-scale problem (think about the number of transistors in a mordern CPU chip as the problem size). Since we have to deal with many aspects of CAD algorithm and software development, I have to enjoy research on differential equations and optimization problems in applied mathematics. Besides, I also nurture the habit of being open to the challenges from distributed/parallel computing systems and large-scale numerical algorithms, as well as high performance programming language and compilers. Some of them are still at the early stages, which I have been growing in our CS department.


  • Qualcomm FMA Fellowship (2013-2014): one of the four recipients [award].

  • Prestigious Charles Lee Powell Fellowship (2012-2015): for supporting outstanding PhD engineering students.

  • Peking University Wu-Si Scholarship (2011).

Updates (2012 - present)

  • June-Sep. 2015: PhD R&D software architect internship at Ansys, Inc. and Apache Design Solutions Unit, the leading engineering simulation software company, working with Dr. S. McCormick (PhD MIT EECS '89) and Dr. Norman Chang (PhD UC Berkeley EECS '90, Vice President and Senior Product Strategiest of Ansys - Apache Design Solutions Unit), for developing the advanced design automation and analysis techniques to help design morden energy-efficient computing systems in Totem, PathFinder and Redhawk teams.

  • June 2015: (1) Candidacy for the doctoral degree in the Department of Computer Science and Engineering was approved effective June 3, 2015. My first US education degree C. Phil will be awarded. (2) Attended DAC'15, San Fransisco, CA and presented [paper] [slides] [poster].

  • May 27th 2015: Passed the PhD qualification and thesis proposal exam after 25 academic months in UCSD. Committee members: Chung-Kuan Cheng, Li-Tien Cheng, Bo Li, Bill Lin, Yuan Taur.

  • Feb. 2015: One paper got accepted by the top-tier EDA conference ACM/IEEE DAC'15.

  • Nov. 2014: (1) Our journal paper about VLSI physical design placement (ePlace) using one of accelerated gradient methods – Nesterov's optimization algorithm and FFT solver got accepted by the top-tier EDA journal IEEE Trans. CAD (TCAD); (2) Served as the computer system administrator at the VLSI design lab. I am currently the system programmer of the internal system - feynman dot ucsd dot edu.

  • Sep. 2014: Became 3rd year PhD student at CSE Dept., UCSD.

  • June-Sep. 2014, R&D software engineering intern at Synopsys, Inc., the leading software and IP company in EDA: worked with Dr. Z. Tang & D. Liu to help PrimeRail in IC Compiler & PrimeTime and shipped a bunch of code from my summer projects into the product.

  • June 2014: (1) Attended ACM/IEEE DAC 2014, and presented the work [paper] [slides] to simulate power grid network using matrix exponential integrators, Krylov subspace algorithms, and its distributed computation framework. (2) Passed UCSD CSE Ph.D's research exam (Committee members: Prof. Steven Swanson (chair), Prof. Sanjoy Dasgupta, and Prof. Lawrence Saul). (3) Gave a research talk at Synopsys, Inc. (4) Stated to live at the campus of Stanford University at the end of month for the summer.

  • Apr. 2014: Attended UC San Diego Jacob School of Engineering's Research Expo

  • Feb. 2014: One paper got accepted by the top-tier ACM/IEEE Design Automation Conference (DAC) 2014, San Francisco, CA, thanks my co-authors, Dr. Shih-Hung Weng (now a research scientist with Facebook, Inc.) and Jeng-Hau Lin, and Prof. Chung-Kuan Cheng.

  • Dec. 2013: Gave a talk on matrix exponential based circuit simulation in EDA Lab, Tsinghua University, hosted by Prof Wenjian Yu.

  • Sep. 2013: Became 2nd year PhD student.

  • June - Sep. 2013: summer research work with Qualcomm Research.

  • May 2013: Our lab was awarded with Qualcomm FMA Fellowship.

  • Sep. 2012: Joined Computer Science & Engineering Department at UC San Diego as 1st year PhD student.

  • Jul. 2012: Graduated from Peking University, Beijing, China, and finished the joint research work with Tsinghua University.

  • Feb. 2012: Awarded with Charles Lee Powell Fellowship from University of California, USA.

Publications/Papers in pre-published

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(Top-tier journals [J]: TCAD, TED, EDL. Top-tier and good conferences [C]: DAC, ICCAD and DATE, ASP-DAC)

Working on

  • [J] H. Zhuang, W. Yu, I. Kang, R. Coutts, C. K. Cheng, “Stable Explicit Time-Domain Simulation Algorithm Using Matrix Exponentials for Large-Scale Nonlinear Circuits,” (under preparation, information upon request)

Submitted/Under reviews

  • [J] H. Zhuang, W. Yu, S.-H. Weng, I. Kang, X. Zhang, R. Coutts, J. Lu, C. K. Cheng, “Simulation Algorithms with Exponential Integration for Time-Domain Analysis of Large-Scale Power Delivery Networks,” submitted to IEEE Trans. Computer-Aided Design (TCAD). [arXiv]

Published during PhD since 2012/09

  • [J][TCAD15b] Qinggao Mei, Wim Schoenmaker, Shih-Hung Weng, Hao Zhuang, Chung-Kuan Cheng, Quan Chen, “An Efficient Transient Electro-Thermal Simulation for Power Integrated Circuits,” IEEE Trans. Computer-Aided Design (TCAD) [paper]. (accepted) (thermal modeling, circuit simulation, matrix exponential, Krylov subspace).

  • [C][BioCAS15] Jeng-Hau Lin, Hao Liu, Chia-Hung Liu, Phillip Lam, Gung-Yu Pan, Hao Zhuang, Ilgweon Kang, Patrick P. Mercier, Chung-Kuan Cheng, “An Interdigitated Non-Contact ECG Electrode for Impedance Compensation and Signal Restoration,” Proc. IEEE Biomedical Circuits and Systems Conference (BioCAS) 2015. (accepted) (signal processing, sensor, ECG, circuits)

  • [C][DAC15] Hao Zhuang, Wenjian Yu, Ilgweon Kang, Xinan Wang, Chung-Kuan Cheng, “An Algorithmic Framework of Large-Scale Circuit Simulation Using Exponential Integrators,” Proc. ACM/EDAC/IEEE Design Automation Conference (DAC), June 2015 [paper] [slides] [poster]. (acceptance rate: 162/789=20.5%) (circuit simulation, matrix exponential, Krylov subspace, large scale computing).
    - This work solves unsolvable problems in traditional SPICE-level simulation when coupling matrix is relatively denser (for accurately capturing the parasitic effects, e.g., Semiwiki) and hard to be factorized or reduced. Our work solves this at the very fundamental level, the basic formulation.

  • [J][TCAD15a] Jingwei Lu, Hao Zhuang, Pengwen Chen, Hongliang Chang, Chin-Chih Chang, Yiu-Chung Wong, Lu Sha, Dennis Huang, Yufeng Luo, Chin-Chi Teng, Chung-Kuan Cheng, “ePlace-MS: Electrostatics based Placement for Mixed-Size Integrated Circuits,”, IEEE Trans. Computer-Aided Design (TCAD). May 2015. [paper] [software package] (VLSI placement, optimization algorithm, FFT solver application)
    - The DAC14 version nominated for Best Paper Award

  • [C][EMC15] Hao Zhuang, Xinan Wang, Ilgweon Kang, Jeng-Hau Lin, Chung-Kuan Cheng, “Dynamic Analysis of Power Delivery Network with Nonlinear Components Using Matrix Exponential Method,” Proc. IEEE EMC and SI, March 2015 [paper]. (power delivery network, power grid, circuit simulation, matrix exponential, large scale computing)

  • [C][DAC14] Hao Zhuang, Shih-Hung Weng, Jeng-Hau Lin, Chung-Kuan Cheng, “MATEX: A Distributed Framework for Transient Simulation of Power Distribution Networks,” Proc. ACM/EDAC/IEEE Design Automation Conference (DAC), June 2014. [paper] [slides] [poster] (acceptance rate: 174/787 = 22.1%) (power delivery network, distributed computing algorithm, circuit simulation, matrix exponential, large scale computing)

  • [J][TCAD13] Wenjian Yu*, Hao Zhuang, Chao Zhang, Gang Hu, and Zhi Liu, “RWCap: A floating random walk solver for 3-D capacitance extraction of VLSI interconnects,” IEEE Trans. Computer-Aided Design (TCAD), March, 2013. [paper] [software package] (chip interconnect, extraction and modeling, statistical algorithm, random sampling)
    - *: Hao Zhuang (1st student author)'s research advisor during this work.
    - Nominated for TCAD's Donald O. Peterson Best Paper Award 2014 and Listed as TCAD popular papers

  • [J][SMPT13] Wenjian Yu, Kuangya Zhai, Hao Zhuang, Junqing Chen, “Accelerated floating random walk algorithm for the electrostatic computation with 3-D rectilinear-shaped conductors,” Elsevier Simulation Modelling Practice and Theory, 34(5): 20-36, 2013. [paper] (chip interconnect, extraction and modeling, GPU computing)

  • [C][DATE13] Kuangya Zhai, Wenjian Yu, Hao Zhuang, “GPU-Friendly floating random walk algorithm for capacitance extraction of VLSI interconnects,” in Proc. IEEE Design, Automation & Test in Europe (DATE), Mar. 2013, pp. 1661-1666. [paper] (chip interconnect, extraction and modeling, GPU computing)

  • [C][ICCCAS13] Hao Zhuang, Jingwei Lu, Kambiz Samadi, Yang Du and Chung-Kuan Cheng, “Performance-Driven Placement for Design of Rotation and Right Arithmetic Shifters in Monolithic 3D ICs,” Proc. IEEE ICCCAS, Oct. 2013. [paper] [slides] (VLSI placement, optimization algorithm, 3D-IC, low power design)

  • [C][ICCCAS13a] Haibing Su, Hao Liu, Shih-Hung Weng, Hui Wang, Aliasgar Presswala, Hao Zhuang, Jeng-Hau Lin, Patrick Mercier, Chung-Kuan Cheng, “A non-contact biopotential sensing system with motion artifact suppression,” Proc. IEEE ICCCAS, Oct. 2013. (sensor, ECG, circuit)

  • [C][ASICON13] Hao Zhuang, Shih-Hung Weng, Chung-Kuan Cheng, “Power Grid Simulation using Matrix Exponential Method with Rational Krylov Subspaces,” Proc. IEEE Intl. Conf. on ASIC (ASICON), Oct. 2013. Updated on [arXiv] [paper] [slides] (power delivery network, circuit simulation, numerical algorithm)

Selected Papers Published Before PhD study 2012/09: Before coming to UC San Diego, it was my privilege to work with my collaborators, including Prof. Wenjian Yu and Prof. Zuochang Ye (Tsinghua University); Prof. Mansun Chan, Dr. Lining Zhang and Dr. Chenyue Ma (HKUST, Hong Kong University of Science and Techology); Prof. Xinnan Lin and Prof. Jin He (Peking University); Prof. Yu Cao (ASU, Arizona State University), Ben Gu (now at Cadence Design Systems), Zhiyu Xu (now at Nvidia), etc.

  • [C][ASPDAC12] Hao Zhuang, Wenjian Yu, Gang Hu, Zhi Liu, Zuochang Ye, “Fast floating random walk algorithm for multi-dielectric capacitance extraction with numerical characterization of Green's functions,” in Proc. ACM/IEEE Asia & South Pacific Design Automation Conf. (ASP-DAC), Jan. 2012, pp. 377-382. [paper] (chip interconnect, extraction and modeling, random algorithm, multithreaded programming)

  • [C][ASICON11] Hao Zhuang, Wenjian Yu, Gang Hu, Zuochang Ye, “Numerical characterization of multi-dielectric Green's function for floating random walk based capacitance extraction,” Proc. IEEE Intl. Conf. ASIC (ASICON), Oct. 2011, pp. 361-364. [paper] [slides] (chip interconnect, extraction and modeling, random algorithm, field solver)

  • [C][ASICON11] Gang Hu, Wenjian Yu, Hao Zhuang, Shan Zeng. “Efficient floating random walk algorithm for interconnect capacitance extraction considering multiple dielectrics.” Proc. IEEE Intl. Conf. ASIC (ASICON), Oct. 2011, pp. 834-837. (chip interconnect, extraction and modeling, random algorithm, field solver)

  • [C][ASICON11] Zhiyu Xu, Xinnan Lin, Hao Zhuang, Bo Jiang, Haijun Lou, Jin He. “A new nonlinear parameterized model order reduction technique combining the interpolation method and Proper Orthogonal Decomposition.” Proc. IEEE Intl. Conf. ASIC (ASICON), 2011 pp. 886-889. (model order reduction, circuit simulation)

  • [C][Nanotech11] Zhiyu Xu, Hao Zhuang, Bo Jiang, Ben Gu, Xinnan Lin, Jin He, Yu Cao, Yang Zhang, Guozeng Wang, Peigang Deng, Xiaojin Zhao, Yang Zhang, Yong Ma, Wen Wu, Wenping Wang, “An Efficient Iterative Grid Selection Strategy for Time-Mapped Harmonic Balance Method.” NSTI Nanotech 2011, vol. 2., pp. 671-674. (circuit simulation)

  • [J][JCTN11] Jin He, Min Shi, Lining Zhang, Jian Zhang, Chi Liu, Hao Zhuang, and Mansun Chan, “Computation Efficient Yet Accurate Surface Potential Based Analytic Model for Symmetric DG MOSFETs to Predict Current-Voltage Characteristics”, Journal of Computational and Theoretical Nanoscience, vol. 8, no. 8, August 2011, pp. 1548-1551 (semiconductor infrastructure, device for computer architecture)

  • [J][JCTN11] Min Shi, Jin He, Lining Zhang, Jian Zhang, Zhiwei Liu, Wen Wu, Wenping Wang, Yong Ma, Xukai Zhang, Hao Zhuang. “A Physics Based Yet Computation Efficient Core Model for Undoped Surrounding-Gate MOSFET Current–Voltage and Capacitance–Voltage Characteristics Prediction.” Journal of Computational and Theoretical Nanoscience, vol. 8, no. 9, 2011, pp. 1732-1738. (semiconductor infrastructure, device for computer architecture)

  • [J][EDL11] Min Shi, Jin He, Lining Zhang, Chenyue Ma, Xingye Zhou, Haijun Lou, Hao Zhuang, Ruonan Wang, Yongliang Li, Yong Ma, Wen Wu, Wenping Wang, Mansun Chan, “Zero-mask contact fuse for one-time-programmable memory in standard CMOS processes.” IEEE Electron Device Letters (EDL), vol. 32, no. 7, July 2011, pp. 955-957. (semiconductor infrastructure, memory, device for computer architecture)

Other Articles

  • Hao Zhuang, “FFT multiplication/convolution application,” pp. 5-7 of [pdf] for the problem 3 in [pdf].

  • Hao Zhuang, Jin Wang, “Sparse matrix-vector multipciation (SpMV) with MPI,” Dec. 2012 [report].

  • Hao Zhuang, “Hacking SPICE” [link].

Descriptions of Selected Research Projects

  • Circuit Simulation Algorithms and its Parallel/Distributed Processing, Applications of Power Network Analysis (Mar. 2013 - present)
    Description: “To analyze and verify VLSI systems via full circuit simulation and to demonstrate vastly improved scalability in order to raise the quality and scope of predictive circuit modeling. VLSI circuit simulation has become critical due to interconnect dominance of advanced fabrication technologies. Functional modules are integrated through substrates and connected by wires with parasitics. A simulation of the whole system will empower designers with a full grasp of the transient behavior of the circuits.” Keywords: Matrix Exponential, Krylov Subspace, Distributed Computing, Parallel Computing, VLSI Design and Analysis, Numerical Algorithms, Differential Equations, Compact Modeling, GPU, Power Distribution Networks, Power Delievery Networks, ASIC design.
    Advisor: Prof. Chung-Kuan Cheng.
    Academic collaborators: Dr. Shih-Hung Weng, Ilgweon Kang, Prof. Wenjian Yu, Dr. Quan Chen.
    Papers: [DAC15] [TCAD15b] [DAC14] [EMC15] [ASICON13]
    Stay tuned

  • Design and Design Automations in Placement, Synthesis of 2D/3D-ICs (Jun. 2013 - present) [ePlace project website]
    Description: Design automation algorithms to investigate the floorplanning and synthesis for 2D/3D integrated circuits. The goal is to extract and manipulate the topology of 2D/3D geometry for physical layout. We mimic the electrostatics for placement problem, and use optimization algorithms to reduce the compoiste objective functions. The placement solver also smartly adopts fast Fourier transformation (FFT) to accelerate its optimization process (The 2D placement algorithm research is supported by Cadence Design Systems). The design automation research for future computer architecture using 3D-ICs is also supported by Qualcomm FMA fellowship 2013. Keywords: Physical Design, Placement, ePlace, Nesterov's Method, FFT, Linear and Nonlinear Programming, Combinatorial Optimization, VLSI Design, VLSI Synthesis, Computer Architecture, Interconnect Network.
    Advisor: Prof. Chung-Kuan Cheng.
    Academic collaborators: Dr. Jingwei Lu, Ilgweon Kang.
    Papers: [TCAD15a] [ICCCAS13]

  • Stochastic Algorithms for VLSI chip parasitic extraction field solver (Feb. 2011 - Jul. 2012) [RWCap project website] and [RWCap2 new project webiste]
    Description: To extract capacitance parameters in VLSI design by devising floating random walk algorithms. This method improves scalability and efficiency for large-scale numerical problems. Some pratical software packages have been developed. Keywords: Floating Random Walk Algorithms, Multi-thread Programming, GPU, 3D Space Management, Importance/Stratified Sampling, Monte Carlo Algorithm.
    Advisor: Prof. Wenjian Yu.
    Academic collaborators: Chao Zhang, Kuangya Zhai, Zhi Liu, Gang Hu, Prof. Zuochang Ye.
    Papers: [TCAD13] [SMPT13] [DATE13] [ASPDAC12] [ASICON11]

Academic Software, Systems and Tools

  1. RWCap: a multi-threaded 3-D floating random walk algorithm based capacitance solver for VLSI Parastic extraction (Implementation using C++, and POSIX pthread) Related Express

    1. RWCap (v1)
      Contributors: Hao Zhuang, Chao Zhang, Gang Hu, Kuangya Zhai, Zhi Liu, Ting Dai. Supervisor: Wenjian Yu.

    2. RWCap (v2)
      Contributors: Chao Zhang, Hao Zhuang. Supervisor: Wenjian Yu
      Please check Prof. Wenjian Yu's page for the latest updates.

  2. ePlace: a electrostatics based placmeent using FFT and accelerated gradient method – Nesterov's optimization algorithm.

    1. 2D Placement
      Active developers: Jingwei Lu, Ilgweon Kang, Hao Zhuang. Supervisor: Chung-Kuan Cheng.

    2. 3D Placement
      Active developers: Ilgweon Kang, Jingwei Lu, Hao Zhuang. Supervisor: Chung-Kuan Cheng.

  3. MATEX: a SPICE-like circuit simulation using matrix exponential integration

    1. It has been under in-house test.


Research and Working Expeirence


  • IEEE student memeber since 2011.

  • ACM student memeber since 2014.

  • SIAM student memeber since 2014.

  • External reviewer, ACM/IEEE Design Automation Conference (DAC).

  • External reviewer, ACM/IEEE International Symposium on Physical Design (ISPD).

  • Reviewer, IEEE Transaction on Computer Aided Design (TCAD).



Selected Courses

Computer Science (CS)

– Theory

– System

– Application

Mathematics (MATH)

Electrical Engineering (EE)

My education background dangles in EECS and Applied Math. Thanks to the people around in CS/EE/Math departments and even my roommates, who bring to me the beauty of theoritical parts of kernel solvers, numerical solvers, optimizers, machine learning as well as their applications on computer systems designs, programming.

For programming language, I am a fan of C/C++, MATLAB, Python, Go. sometimes I use Haskell, Perl, Javascript and Node.js and play around with LLVM for Compiler and Computer System and Architecture. Above all, I like the quote from Prof. Alan Eldeman “… It's the human time that in the end matters the most.” by MIT News HPC with ease.

I also like dropbox product, since it helped me recover all my important documents after I lost my bag and computer in China.

Links and Useful Notes (at least to me)

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