Massively Heterogeneous Multiprocessors

Utilization Wall:

In the current regime, transistor density and switching speed continues to increase with each generation of Moore’s Law, but limits on threshold voltage scaling have stopped the downward scaling of per-transistor switching power. Consequently, the fraction of the chip that can be used at full speed simultaneously decreases by half with each process generation. We term this phenomenon the Utilization Wall.

Goal:

Massive Heterogeneity to attack the performance scaling issues caused by THE POWER Wall

Arsenal Design Philosophy:

Arsenal aims to tackle the exponentially worsening utilization wall problem with massive heterogeneity. The project focuses on all the design aspects of these multiprocessors - automatically designing and testing specialized processors, integrating them with general-purpose processors, memory sub-system, programming such a heterogeneous system etc.