Current Project Abstracts

  1. High Content Optical Mapping for Cardiac Electrophysiology: Hundreds of thousands of people die from arrhythmia-induced cardiac sudden death in the U.S. every year. Cardiac electrophysiology is important for understanding, diagnosing and treating electrical arrhythmias of the heart. Optical mapping is an increasingly popular tool for experimentally visualizing the electrical activity in the heart. Optical mapping employs a transmembrane voltage sensitive fluorescent dye and measures the electrical activity through a high speed image sensor. These systems allow researchers to visualize action potential propagation on the surface for the heart with high spatial and temporal resolution. One can record the full action potential from many locations simultaneously so it is possible to see the shape of the action potentials, as well as the spread of activation and repolarization.
    Optical mapping is a computationally intensive procedure and present-day research is substantially hindered by the significant amount of time required to perform analysis even on the smallest amount of data; a few seconds of recorded data requires many hours of computation time. In this project, we are developing a custom hardware compute engine that can perform optical mapping in real-time, i.e., over several orders of magnitude faster than the current state of the art. This will open new avenues of research that ultimately enable closed-loop feedback control of cardiac function that is not feasible using global measures of electrophysiology such as the electrocardiogram (ECG).

  2. Automation of stem cell derived cardiomyocyte selection and analysis:
    • Development of a system that quickly and accurately detects beating as well as labeled cardiomyocytes, providing either rapid feedback of cell location or image acquisition;
    • Development of methods to identify mature hESC-derived cardiomyocytes by identifying desmoplakin at the cell boundaries and searching for striated muscle proteins.

  3. Hardware Acceleration of Mean Variance Framework for Optimal Asset Allocation: Asset classes respond differently to shifts in financial markets, thus an investor can minimize the risk of loss and maximize return of his portfolio by diversification of assets. Increasing the number of diversified assets in a financial portfolio significantly improves the optimal allocation of different assets giving better investment opportunities. However, a large number of assets require a significant amount of computation that only high performance computing can currently provide. Because of the highly parallel nature of Markowitz' mean variance framework (the most popular approximation approach for optimal asset allocation) an FPGA implementation of the framework can also provide the performance necessary to compute the optimal asset allocation with a large number of assets. In this work, we present an FPGA implementation of Markowitz' mean variance framework and show it has a potential performance ratio of 221X over a software implementation.

  4. Hardware Acceleration of Black-Scholes Option Pricing Model: The ever increasing volume of financial data, increase in the client portfolios and demand for faster results have led financial organizations to seek high performance computing solutions. The addition of FPGAs (Field-Programmable Gate Arrays), as specially designed hardware units, to existing high performance computers can boost financial application performance through their ability to execute complex tasks in parallel. Financial instruments such as options are highly diversified and flexible entities that are traded both on the stock exchanges and over-the counter markets. The value of the options depends on the future value of one or more underlying assets, for example value of several stocks. The whole process of obtaining this value is known as Option-Pricing. The Chicago Board Options Exchange (CBOE) reported that 2009 trading volume exceeded one billion contracts for the second consecutive year. It is not unusual today for a single option to be a function of 20 or more underlying assets valued at 100 or more points in time, yielding an integral over 2000+ dimensions. Thus achieving the optimum price for options can involve solving many mathematical and computational intensive problems which takes a lot of CPU time to compute. Hence, we present a new working architecture which is a real-time solution for option pricing using Monte Carlo Methods for simulations. Our model is based on the Black-Scholes equations on option pricing. We show that our specially designed FPGA can achieve an output which could be 300X faster than the current implementation.

  5. Hardware Security - Gate Level Information Flow Tracking (GLIFT): In high assurance systems, such as aircraft control and banks, ensuring non-interference between trusted and untrusted data is crucial. Conventional secure systems build hardware minimal security consideration. Top-down software approaches make it difficult to prove the non-interference in such systems due to the complexity of software. A bottom-up hardware approach enforces non-interference by tracking information flow at the gate level. Gate level information flow tracking (GLIFT) can be used to enforce non-interference in embedded systems. We perform research on theoretical basis for GLIFT by introducing essential definitions, properties as well as various GLIFT logic generation methods. We also provide solutions to the problem of a frequently used GLIFT logic generation method being overly conservative. Using GLIFT, we have exposed vulnerabilities in I2C and USB. We are currently extending the GLIFT logic to analyze any finite state machine (FSM).

  6. High Level Synthesis Tool Design - S&E: Simulate and Eliminate Integrated circuit technology will continue to follow Moore's Law for the foreseeable future, and multi-core architectures will provide a means to increase performance while keeping the power consumption under control. Furthermore, we are seeing an increasing trend towards application specific processing, particularly in embedded computing devices that have stringent performance requirements. Achieving the desired power/energy, area and throughput constraints requires careful tuning of the underlying architecture. There are many architectural design choices that need to be made while implementing the application specific, multi-core architectures. Not only does generating the multi-core architecture for a given set of requirements involve tedious work, but performing design space exploration to find the optimum hardware design is also a time consuming process. Therefore, a high level design tool for design space exploration and fast prototyping of multi-core architectures is essential.

    In this project, we create a tool, called Simulate & Eliminate (S&E), which generates completely synthesizable HDL for multi-core architectures. S&E first generates a general purpose, multi-core architecture. Then, the provided application(s) are simulated on this general purpose architecture and the unneeded functionality is eliminated resulting in application specific architecture. We specifically aim to create this tool for digital signal processing applications and test S&E by using it to develop architectures for wireless underwater modems, smart cameras, and MIMO OFDM radios.

Research Articles

Journal Articles

[24] GUSTO: An Automatic Generation and Optimization Tool for Matrix Inversion Architectures, Ali Irturk, Bridget Benson, Shahnam Mirzaei and Ryan Kastner, ACM Transactions on Embedded Computing Systems.

[23] Simulate and Eliminate: A Methodology to Design Application Specific Multi-Core Architectures for Matrix Computations, Ali Irturk, Janarbek Matai, Jason Oberg, Jeffrey Su and Ryan Kastner, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[22] Theoretical Fundamentals of Gate Level Information Flow Tracking, Vinnie Hu, Jason Oberg, Ali Irturk, Mohit Tiwari, Timothy Sherwood, Ryan Kastner, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[21] An Optimized Algorithm for Leakage Power Reduction of Embedded Memories on FPGAs Through Location Assignments, Shahnam Mirzaei, Yan Meng, Farahnaz A. Nezhad, Ali Irturk, Timothy Sherwood, Ryan Kastner, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Conferences

[20] High Content Optical Mapping for Cardiac Electrophysiology, Ali Irturk, Sam Wood, Alex Indaco, Ryan Kastner, International Workshop on Biomedical System Design (BSD 2010).

[19] Automation of Stem Cell derived Cardiomyocyte Selection and Analysis, Ali Irturk, Ryan Kastner, International Workshop on Biomedical System Design (BSD 2010).

[18] GPU Acceleration of Optical Mapping Algorithm for Cardiac Electrophysiology, Pingfan Meng, Ali Irturk, Ryan Kastner, Under Review, The 19th Annual IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM 2011).

[17] Design and Implementation of an FPGA-based Real-Time Face Recognition System, Janarbek Matay, Ali Irturk, Ryan Kastner, In Proceedings of the 19th Annual IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM 2011).

[16] Analyzing Information Flows in Bus Protocols Using Gate Level Information Flow Tracking, Jason Oberg, Vinnie Hu, Ali Irturk, Mohit Tiwari, Timothy Sherwood, Ryan Kastner, In Proceedings of the Design Automation Conference (DAC 2011).

[15] Generating Precise Logic for Gate Level Information Flow Tracking, Vinnie Hu, Jason Oberg, Ali Irturk, Mohit Tiwari, Timothy Sherwood, Ryan Kastner, Under Review, Design Automation Conference (DAC 2011).

[14] Theoretical Analysis of Gate Level Information Flow Tracking, Jason Oberg, Vinnie Hu, Ali Irturk, Mohit Tiwari, Timothy Sherwood, Ryan Kastner, In Proceedings of the Design Automation Conference (DAC 2010).

[13] Xquasher: A Tool for Efficient Computation of Multiple Linear Expressions, Arash Arfaee, Ali Irturk, Nikolay Laptev, Ryan Kastner, Farzan Fallah, In Proceedings of the Design Automation Conference (DAC 2009).

[12] Energy Benefits of Reconfigurable Hardware for use in Underwater Sensor Nets, Bridget Benson, Ali Irturk, Junguk Cho, Ryan Kastner, In Proceedings of the 16th Reconfigurable Architectures Workshop (RAW 2009), May 2009.

[11] Architectural Optimization of Decomposition Algorithms for Wireless Communication Systems, Ali Irturk, Bridget Benson, Nikolay Laptev and Ryan Kastner, In Proceedings of the IEEE Wireless Communications and Networking Conference (WCNC 2009), April 2009.

[10] FPGA Acceleration of Mean Variance Framework for Optimum Asset Allocation, Ali Irturk, Bridget Benson, Nikolay Laptev and Ryan Kastner, In Proceedings of the Workshop on High Performance Computational Finance at SC08 International Conference for High Performance Computing, Networking, Storage and Analysis, November 2008.

[9] Automatic Generation of Decomposition based Matrix Inversion Architectures, Ali Irturk, Bridget Benson and Ryan Kastner, In Proceedings of the IEEE International Conference on Field-Programmable Technology (ICFPT), December 2009.

[8] Survey of Hardware Platforms for an Energy Efficient Implementation of Matching Pursuits Algorithm for Shallow Water Networks, Bridget Benson, Ali Irturk, Junguk Cho, and Ryan Kastner, In Proceedings of the The Third ACM International Workshop on UnderWater Networks (WUWNet), in conjunction with ACM MobiCom 2008, September 2008.

[7] Design Space Exploration of a Cooperative MIMO Receiver for Reconfigurable Architectures, Shahnam Mirzaei, Ali Irturk, Ryan Kastner, Brad T. Weals and Richard E. Cagley, In Proceedings of the IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP), July 2008.

[6] An FPGA Design Space Exploration Tool for Matrix Inversion Architectures, Ali Irturk, Bridget Benson, Shahnam Mirzaei and Ryan Kastner, In Proceedings of the IEEE Symposium on Application Specific Processors (SASP), June 2008.

Theses and Others

[5] GUSTO: General architecture design Utility and Synthesis Tool for Optimization, Ali Irturk, PhD Thesis, Department of Computer Science and Engineering, University of California, San Diego, September 2009. Advisor: Ryan Kastner.

[4] Implementation of QR Decomposition Algorithms using FPGAs, Ali Irturk, MS Thesis, Department of Electrical and Computer Engineering, University of California, Santa Barbara, June 2007. Advisor: Ryan Kastner.

[3] An Optimization Methodology for Matrix Computation Architectures, Ali Irturk, Bridget Benson, and Ryan Kastner, UCSD Technical Report, CS2009-0936.

[2] FPGA Implementation of Adaptive Weight Calculation Core Using QRD-RLS Algorithm, Ali Irturk, Shahnam Mirzaei and Ryan Kastner, UCSD Technical Report, CS2009-0937.

[1] An Efficient FPGA Implementation of Scalable Matrix Inversion Core using QR Decomposition, Ali Irturk, Shahnam Mirzaei and Ryan Kastner, UCSD Technical Report, CS2009-0938.