Ali U. Irturk
Ph.D. at University of California, San Diego
M.A. and M.S. at University of California, Santa Barbara
B.A. and B.S. at Turkish Naval Academy
FPGA Acceleration of Mean Variance Framework for Optimal Asset Allocation
      Asset allocation is the core part of portfolio management. With asset allocation, an investor distributes his wealth across different asset classes which include
different securities such as bonds, equities, investment funds, derivatives, etc. in a given market to form a portfolio. Because each asset class responds differently to shifts in financial markets,
an investor can minimize the risk of loss and maximize the return of his portfolio by diversifying his assets.
      Increasing the number of diversified assets in a financial portfolio significantly improves the optimal allocation of different assets giving better investment opportunities.
The goal of the portfolio manager in a financial institution is to provide the asset allocation with the greatest return for some level of risk for investors.
Adding new assets to a portfolio shifts the frontier to the upper left which gives better return opportunities with
less risk compared to the lower number of assets portfolios.
The required steps for optimal asset allocation are shown in (a), (b) and (c). After the required inputs to the mean
variance are generated in (a), computation of the efficient frontier and determination of the highest utility portfolio are shown in (b)
and (c) respectively. This figure also presents the inputs and outputs provided to the user.
      However, a large number of assets require a significant amount of computation that only high performance computing can currently provide. Because of the highly
parallel nature of Markowitz' mean variance framework an FPGA implementation of the framework can also provide the performance necessary to compute the optimal asset allocation
with a large number of assets.
      In this work, we present:
1) A detailed description of the mean variance framework for optimal asset allocation, incorporating investor objectives and satisfaction indices used in practical
implementations;
The procedure to generate required inputs is described. The numbers 1-5 refers to these computation steps which are
explained in paper subsections in more detail.
2) Identification of bottlenecks for the mean variance framework which can be adapted to work in hardware;
We run two different test while holding all but one variable constant. We determined that generation of the required input does not
consume significant amount of time. On the other hand, step 1 and 2 of the mean variance framework consumes significant amount of
time.
3) Design of the proposed hardware for the FPGA implementation of the mean variance framework;
Parallel parameterizable hardware architecture for the mean variance framework step 2. The Monte-Carlo block,
Utility Calculation Block, and Satisfaction Function Calculator IP core can be easily parallelized.
4) A study of potential performance improvements through simulations of the hardware architectures and a comparison between a software
implementation running on two 2.4 Ghz Pentium-4 CPUs, and an FPGA architecture, showing potential performance ratios
of 9.6 × and 221 × for different steps.
Possible speed-ups for "generation of the required inputs - phase 5" and "mean variance framework Step 2".
You can find more detailed information about this research by moving through tabs or reading our paper.