I am a Ph.D student at the Computer Science & Engineering Department of University of California, San Diego. My advisor is professor Alex Orailoglu, who leads the Architecture, Reliability & Testing (ART) group. My research interests include VLSI design & testing, design for testability, and silicon failure analysis. My thesis work is focused on the design & test optimization techniques for IR-drop failure mitigation & yield improvement. I am also a staff IC design engineer in Broadcom Corporation.

Contact Info:

Education:

B.S. in Electronic Engineering, Tsinghua University, China, 2002
M.S. in Microelectronics, Tsinghua University, China, 2005
Ph.D student, UCSD, 2005 - present

Publications:

Conference Papers

  1. M. Chen and A. Orailoglu, “Diagnosing scan clock delay faults through statistical timing pruning,” Proc. of the IEEE/ACM Design Automation Conference, 2011.
  2. M. Chen and A. Orailoglu, “Diagnosing scan chain timing faults through statistical feature analysis of scan images,” Proc. of the IEEE/ACM Design, Automation and Test in Europe, 2011.
  3. M. Chen and A. Orailoglu, “VDDmin test optimization for overscreening minimization through adaptive scan chain masking,” Proc. of the 28th VLSI Test Symposium, 2010.
  4. M. Chen and A. Orailoglu, “Cost-effective IR-drop failure identification and yield recovery through a failure-adaptive test scheme,” Proc. of the IEEE/ACM Design, Automation and Test in Europe, pp. 63-68, 2010.
  5. M. Chen and A. Orailoglu, “Scan power reduction in linear test data compression scheme,” Proc. of the IEEE/ACM International Conference on Computer-Aided Design, pp. 78-82, 2009.
  6. C. Yang, M. Chen and A. Orailoglu, “Squashing microcode stores to size in embedded systems while delivering rapid microcode accesses,” CODES+ISSS, pp. 249-256, 2009.
  7. M. Chen and A. Orailoglu, “Flip-flop hardening and selection for soft error and delay fault resilience,” Proc. of 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, pp. 49-57, 2009.
  8. M. Chen and A. Orailoglu, “Deflecting crosstalk by routing reconsideration through refined signal correlation estimation,” Proc. of the 19th ACM Great Lakes Symposium on VLSI, pp. 369-374, 2009.
  9. M. Chen and A. Orailoglu, “Test cost minimization through adaptive test development,” Proc. of the 26th IEEE International Conference on Computer Design, pp. 234-239, 2008.
  10. M. Chen and A. Orailoglu, “Circuit-level mismatch modeling and yield optimization for CMOS analog circuits,” Proc. of the 25th IEEE International Conference on Computer Design, pp. 526-532, 2007.
  11. M. Chen and A. Orailoglu, “Improving circuit robustness with cost-effective soft-error-tolerant sequential elements,” Proc. of the 16th IEEE Asian Test Symposium, pp. 307-312, 2007.
  12. M. Chen, H. Haggag and A. Orailoglu, “Decision tree based mismatch diagnosis in analog circuits,” Proc. of the 24th VLSI Test Symposium, pp. 278-285, 2006.
  13. D. Xiang, M. Chen and H. Fujiwara, “Using weighted scan enable signals to improve the effectiveness of scan-based BIST,” Proc. of the 14th IEEE Asian Test Symposium, pp. 126-131, 2005.
  14. D. Xiang, M. Chen, K-W. Li and Y. L. Wu, “Scan-based BIST using an improved scan forest architecture,” Proc. of the 13th IEEE Asian Test Symposium, pp. 88-93, 2004.
  15. M. Chen and D. Xiang, “Pseudorandom scan BIST using improved test point insertion techniques,” Proc. of the 7th IEEE International Conference on Solid-State and Integrated-Circuit Technology, 2004.
  16. D. Xiang, M. Chen, J-G. Sun and H. Fujiwara, “Improving test quality of scan-based BIST by scan chain partitioning,” Proc. of the 12th IEEE Asian Test Symposium, pp. 12-18, 2003.

Journal Papers

    1. M. Chen and A. Orailoglu, “Scan power reduction for linear test compression schemes through seed selection,” IEEE Transactions on VLSI, accepted.
    2. C. Yang, M. Chen and A. Orailoglu, “Squashing code size in microcoded IPs while delivering high decompression speed,” Design Automation for Embedded Systems, vol. 14, no. 3, pp. 265-284, 2010.
    3. D. Xiang, M. Chen and H. Fujiwara, “Using weighted scan enable signals to improve test effectiveness of Scan-Based BIST,” IEEE Transactions on Computers, vol. 56, no. 12, pp. 1619-1628, Dec. 2007.
    4. D. Xiang, M. Chen, J-G. Sun and H. Fujiwara, “Improving test effectiveness of scan-based BIST by scan chain partitioning,” IEEE Transactions on CAD of ICAS, vol. 24, pp. 916- 927, June 2005.
    5. D. Xiang, M. Chen and J.-G. Sun, “Scan BIST with biased scan test signals,” Science in China, 2008.
    6. M. Chen and D. Xiang, “BIST technique based on scan forest architecture,” Computer Engineering & Science (Chinese version), vol. 27, pp. 36-40, April 2005.

Patents:

    1. D. Xiang, J-G. Sun, M. Chen and S. Gu, “Cost-effective scan architecture and a test application scheme for scan testing with non-scan test power and test application cost,” US Patent number: 6,959,426, Issue Date: 10-25-2005
    2. D. Xiang, J-G. Sun and M. Chen, “Scan-Based self-test structure and method using weighted scan enable signals,” US patent number: 7,526,696, Issue Date: 04-28-2009