Michael B. Taylor

      Assistant Professor
      Computer Science and Engineering
      University of California, San Diego
                                                              

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[Michael Taylor]


I am an assistant professor in the Department of Computer Science and Engineering at the University of California, San Diego. I received a PhD in Electrical Engineering and Computer Science from MIT. My thesis was on the MIT Raw tiled multicore processor, one of the earliest multicore processors, and which was commercialized into the Tilera TILE64 architecture.

I was a rebellious undergraduate in the Dartmouth College CS department, where I pulled together a team of students to build my first machine, the PM IV. It had 72 chips and over 5000 hand-wired connections.

Between the gaps at school, I worked on Apple's NuKernel microkernel, and co-wrote the first version of Connectix Virtual PC, an x86-to-PowerPC dynamic translation engine, which was acquired by Microsoft. I also contributed to the ChipWrights Visual Signal Processor in its earliest stages.

I received the NSF CAREER Award in 2009.

January 2010 Conservation Cores camera ready version ready. If you read one architecture paper this year, read this ASPLOS 2010 Paper.
November 2009 Newsflash! We just released The San Diego Vision Benchmark Suite, a benchmark for the vision application domain, written in MATLAB and clean C. It's available at parallel.ucsd.edu/vision.
November 2009 Newsflash! Our paper, Conservation Cores: Reducing the Energy of Mature Computations, was accepted into ASPLOS 2010.
October 2009 My student, Sravanthi Kota Venkata, presents our IISWC paper on the San Diego Vision Benchmark Suite in Austin, TX.
September 2009 Awarded 150,000 hours of compute time on the San Diego Super Computer TRITON Cluster for the Photon manycore compiler project!
September 2009 Nathan Goulding, Jonathan Babb, and I recently pulled two all-nighters in a row and designed a low-power prototype chip, called the C-core I, which will be the basis for processor designs in future fabrication regimes in which energy is limited by the utilization wall.
July 2009 Successfully passed the FAA written test and landed an airplane four times at Long Beach Airport (LGB)!
June 2009 National Science Foundation CAREER Award: Energy-Efficient Parallel Architectures for Computer Vision.


Current Research


I direct the UCSD Center for Multicore and Manycore Parallelism, which encompasses my group's ongoing projects, including:

Ideal Students for my Research Group

 The kinds of students that will succeed best in my group are those who love to build agressive but elegant systems and tune their performance -- compilers, graphics renderers, simulators, computers, dynamic translation emulators, operating systems, boards or even chips. They like coding, have written a lot of it, and know how to write solid, elegant code (ala Writing Solid Code or The Pragmatic Programmer), and don't mind telling others how to do it -- and maybe have worked at companies on software systems or chip design. They tend to have lots of little side projects and experiments that they have done outside of class. They might enjoy reverse-engineering things as well.


Collaborations


My collaborators here at UCSD include Steven Swanson, Dean Tullsen, Yoav Freund, Serge Belongie, CK Cheng, and the members of Calit2.


I advise or co-advise a group of fantastic graduate students; including:
        Saturnino Garcia     Nathan Goulding
        Anshuman Gupta     Sravanthi Kota Venkata
        Donghwan Jeon     Patrick Li
        Christopher Louie     Scott Ricketts
        Jack Sampson     Gopi Tummala
        Ganesh Venkatesh

My past advisees and co-advisees include:

Teaching
Fall 2009 CSE 291: Manycore System Design
Winter 2009 CSE 240A: Principles of Computer Architecture
Fall 2008 CSE 141: Introduction to Computer Architecture
Fall 2008 CSE 141L: Design and Implement Your Own Processor
Spring 2008 CSE 141: Introduction to Computer Architecture
Spring 2008 CSE 141L: Design and Implement Your Own Processor
Winter 2008 CSE 240B: Advanced/Parallel Computer Architecture
Fall 2007 CSE 291: Design of Concurrent VLSI Architectures
Spring 2007 CSE 141: Introduction to Computer Architecture
Spring 2007 CSE 141L: Design and Implement Your Own Processor
Fall 2006 CSE 240A: Principles of Computer Architecture
Spring 2006 CSE 240B: Advanced Graduate Computer Architecture

Programming Team

 I am the coach for the 2009 UCSD ACM Programming Team, and arranged the UCSD 2009 Fall Programming Contest. There will be a 2010 Winter Programming Contest, as well.

I was the coach for the 2007 UCSD ACM Programming Team and arranged (along with help from Michael Vrable and many others) the UCSD 2007 Fall Programming Contest. The UCSD ACM Team placed 2nd out of a field of 63 teams which included schools like CalTech, Harvey Mudd, USC, UCLA, UCSB, UNLV, and UCI. UCSD was the only school to have two teams place in the top five.

I also arranged (along with help from many others) the UCSD 2006 Fall Programming Contest and coached the 2006 ACM Team, which placed 6th out of 74 teams.


Previous Research

 As one of the lead students in the MIT Raw project, I led the design and implementation of the Raw microprocessor, which targeted the leading VLSI technology of the time. I also contributed heavily to almost all of the software systems that we built to support the microprocessor.

Raw was one of the earliest fabricated multicore processors, with 16 cores on a single die, back in 2002. The purpose of Raw was to demonstrate architectural solutions to scalability problems in modern day microprocessors. The Raw architecture exposes the transistor resources of VLSI chips through the tile abstraction, the pin resources through the I/O port abstraction, and the wiring resources through on-chip networks.

Because the Raw architecture exposed the on-chip resources more effectively than existing sequential architectures (for instance the P6 micro-architecture, the basis of the Pentium-M), Raw was able to outperform Intel desktop processors, implemented with better process technology, across a variety of applications.

One of the key ideas that came out of the Raw research was the formulation of the Scalar Operand Network (SON), a unique class of sub-nanosecond network responsible for routing operands between functional units and memories in a distributed microprocessor.

My team implemented the 16-tile Raw microprocessor, shown to the upper-left, in IBM's SA-27E 180 nm 6-layer Cu ASIC process. The 18.2 mm x 18.2 mm chip was, at least at the time, the largest design that the IBM ASIC division had targeted for SA-27E. Each tile contains computing power equivalent to a single-issue pipelined processor. We taped out the chip in August '02, and received prototypes back in late October '02. The motherboard was assembled January '03. A supercomputer prototype, based on 4-chip boards, that scaled to 64 Raw chips (1024-issue) was constructed.

More pictures are available here.



Downloads


Selected Publications


        Conservation Cores, Utilization Wall and Massively Heterogeneous, Low Power Architectures - Top Reads

          Conservation Cores: Reducing the Energy of Mature Computations.
          Ganesh Venkatesh, John Sampson, Nathan Goulding, Saturnino Garcia, Slavik Bryskin, Jose Lugo-Martinez,
          Steven Swanson, and Michael Bedford Taylor.
          Architectural Support for Programming Languages and Operating Systems, March 2010. (pdf)

          More coming soon!

        Processors for Computer Vision - Top Reads

          SD-VBS: The San Diego Vision Benchmark Suite.
          Sravanthi Kota Venkata, Ikkjin Ahn, Donghwan Jeon, Anshuman Gupta, Christopher Louie, Saturnino Garcia, Serge Belongie, and Michael Bedford Taylor.
          IEEE Interational Symposium on Workload Characterization, October 2009. (pdf) (Download SD-VBS)

        Program Analysis, Transformation, Parallelization and Verification - Top Reads

          Several papers submitted early 2010!

          Runtime checking for program verification.
          Karen Zee, Viktor Kuncak, Michael Taylor, and Martin Rinard.
          7th International Workshop, RV 2007, Vancover, Canada, March 13, 2007, Revised Selected Papers.
          Lecture Notes on Computer Science, Springer Berlin, vol. 4839/2007, p. 202-213.

        Interconnection Network Optimization - Top Reads

          Energy and Switch Area Optimizations for FPGA Global Routing Architectures
          Yi Zhu, Yuanfang Hu, Michael Taylor, and Chung-Kuan Cheng
          ACM Transactions on Design Automation of Electronic Systems, January 2009. (pdf)

          Advancing Supercomputer Performance Through Interconnection Topology Synthesis.
          Yi Zhu, Michael Taylor, Scott B. Baden and Chunk-Kuan Cheng
          International Conference on Computer-Aided Design, November 2008. (pdf)

        Tiled Architectures - Top Reads

          Tiled Microprocessors.
          Michael B Taylor
          PhD Thesis, Massachusetts Institute of Technology, February 2007. (pdf)

          The Raw Microprocessor: A Computational Fabric for Software Circuits and General Purpose Programs,
          by Michael B Taylor, Jason Kim, Jason Miller, David Wentzlaff, Fae Ghodrat, Ben Greenwald, Henry Hoffman, Jae-Wook Lee, Paul Johnson, Walter Lee, Albert Ma, Arvind Saraf, Mark Seneski, Nathan Shnidman, Volker Strumpen, Matt Frank, Saman Amarasinghe and Anant Agarwal.
          IEEE Micro, March/April 2002. (pdf)

          Evaluation of the Raw Microprocessor: An Exposed-Wire-Delay Architecture for ILP and Streams,
          by Michael B Taylor, Walter Lee, Jason Miller, David Wentzlaff, Ian Bratt, Ben Greenwald, Henry Hoffmann, Paul Johnson, Jason Kim, James Psota, Arvind Saraf, Nathan Shnidman, Volker Strumpen, Matt Frank, Saman Amarasinghe, and Anant Agarwal.
          Proceedings of the International Symposium on Computer Architecture, June 2004. (pdf)

          Baring it all to Software: Raw Machines,
          by Elliot Waingold, Michael Taylor, Devabhaktuni Srikrishna, Vivek Sarkar, Walter Lee, Victor Lee, Jang Kim, Matthew Frank, Peter Finch, Rajeev Barua, Jonathan Babb, Saman Amarasinghe, and Anant Agarwal.
          IEEE Computer, September 1997, pp. 86-93.  (pdf)
           

        Scalar Operand Networks - Top Reads



          Scalar Operand Networks,
          by Michael B Taylor, Walter Lee, Saman Amarasinghe, and Anant Agarwal.
          MIT/LCS Technical Memo LCS-TM-644, April 2004.
          IEEE Transactions on Parallel and Distributed Systems (Special Issue on On-chip Networks), February 2005. (pdf) (Appendix pdf)

          Scalar Operand Networks:
          On-chip Interconnect for ILP in Partitioned Architectures          ,
          by Michael B Taylor, Walter Lee, Saman Amarasinghe, and Anant Agarwal.
          Proceedings of the International Symposium on High Performance Computer Architecture, February 2003. (pdf)  

        Tiled Architecture Implementation - Top Reads

          The Raw Specification
          by Michael B Taylor.
          Final Version (5.02). December 2005. (pdf)

          Energy Characterization of a Tiled Architecture Processor with On-Chip Networks,
          by Jason Sungtae Kim, Michael B Taylor, Jason Miller, and David Wentzlaff.
          International Symposium on Low Power Electronics and Design, August 2003.  (pdf)
           
          A 16-issue multiple-program-counter microprocessor with point-to-point scalar operand network,
          by Michael B Taylor, Jason Kim, Jason Miller, David Wentzlaff, Fae Ghodrat, Ben Greenwald, Henry Hoffman, Paul Johnson, Walter Lee, Arvind Saraf, Nathan Shnidman, Volker Strumpen, Saman Amarasinghe, and Anant Agarwal.
          Proceedings of the IEEE International Solid-State Circuits Conference, February 2003. (pdf)

          Design Decisions in the Implementation of a Raw Architecture Workstation,
          by Michael B Taylor.
          MS Thesis, Cambridge, MA, September, 1999. (pdf)

        Book Chapters

          Tiled Multicore Processors.
          Michael B. Taylor, Walter Lee, Jason E. Miller, David Wentzlaff, Ian Bratt, Ben Greenwald, Henry Hoffman, Paul R. Johnson, Jason S. Kim, James Psota, Arvind Saraf, Nathan Shnidman, Volker Strumpen, Matthew I. Frank, Saman Amarasinghe, and Anant Agarwal.
          in Multicore Processors and Systems, Springer,
          edited by Steve Keckler, Kunle Olukotun, and Peter Hofstee, 2009. (link)

          Stream Multicore Processors.
          Michael B Taylor, Walter Lee, Jason Eric Miller, David Wentzlaff, Ian Bratt, Ben Greenwald, Henry Hoffmann, Paul Johnson, Jason Kim, James Psota, Arvind Saraf, Nathan Shnidman, Volker Strumpen, Matt Frank, Rodric Rabbah, Saman Amarasinghe, and Anant Agarwal.
          In Processor Design: System-on-chip Computing for ASICs and FPGAs (hardcover)
          Edited by Jari Nurmi (Editor)          , 2007. (link)

        More Reads
          FPGA Global Routing Architecture Optimization Using a Multicommodity Flow Approach.
          Y. Hu, Y. Zhu, M.B. Taylor, and C.K. Cheng.
          IEEE Int. Conf. on Computer Design, pp. 144-151, 2007. (pdf)

          The RAW Benchmark Suite: Computation Structures for General Purpose Computing,
          by Jonathan Babb, Matthew Frank, Victor Lee, Elliot Waingold, Rajeev Barua, Michael Taylor, Jang Kim, Srikrishna Devabhaktuni, and Anant Agarwal.
          IEEE Symposium on Field-Programmable Custom Computing Machines, Napa Valley, CA, April 1997.  (pdf)
           
        ... More publications ...

Workshops & Talks

        Scalar Operand Networks for Tiled Microprocessors,
        2006 Workshop on On- and Off-Chip Interconnection Networks for Multicore Systems (OCIN) (google video)
        Stanford, CA. December 2006.

        Prototyping Raw,
        International Symposium on Computer Architecture, Workshop on Architectural Research Prototyping (WARP)
        Boston, MA. June 2006.

        Evaluating the Raw Microprocessor: Scalability and Versatility,
        International Symposium on Computer Architecture.
        Munich, Germany. June 21, 2004.

        Evaluating the Raw Microprocessor,
        Boston Area Computer Architecture Workshop.
        Boston, MA. January 30, 2004.

        Scalar Operand Networks,
        International Symposium on High Performance Computer Architecture.
        Anaheim, California. February 12, 2003.

        A 16-issue multiple-program-counter microprocessor with point-to-point scalar operand network,
        IEEE International Solid-State Circuits Conference.
        San Francisco, California. February 11, 2003. (pdf)   (powerpoint with some transcript)

        Panel Chair,
        2nd MIT Computer Architecture Workshop,
        Gloucester, Massachusetts. September 9, 2002.

        The Raw Microprocessor - Exposing Chip Resources to Software,
        Symposium on Hardware/Software Interfacing for Performance Enhancements.
        St Cloud, Minnesota. April 26, 2002.

        The Raw Processor - A Scalable 32-bit Fabric for Embedded and General Purpose Computing,
        Hotchips XIII.
        Palo Alto, California. August 21, 2001. (pdf , powerpoint with transcript)
         

Technology Policy Advocacy

Software

        A tool for deionization, which enables application embedding and improved benchmark precision.


Miscellaneous


Mailing Address



            

       Prof. Michael B. Taylor
      Dept. of Computer Science and Engineering
      University of California, San Diego
      9500 Gilman Drive EBU 3b-4110 MC 0404
      La Jolla, CA 92093-0404