![Michael Taylor]](mbt_photo_14_z_480.jpg)
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Michael B. Taylor Assistant Professor Computer Science and Engineering University of California, San Diego
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I am an assistant professor in the Department of Computer Science and Engineering at the University of California, San Diego. I started in February 2006. I received a PhD in Electrical Engineering and Computer Science from MIT. I was lead architect of the 16-core MIT Raw tiled multicore processor, one of the earliest multicore processors, which was commercialized into the Tilera TILE64 architecture. My dissertation can be found here.
I was a rebellious undergraduate in the Dartmouth College CS department, where I pulled together a team of students to build my first machine, the PM IV. It had 72 chips and over 5000 hand-wired connections.
Between the gaps at school, I worked on Apple's NuKernel microkernel, and co-wrote the first version of Connectix Virtual PC, an x86-to-PowerPC dynamic translation engine, which was acquired by Microsoft. I also contributed to the ChipWrights Visual Signal Processor in its earliest stages.
I received the NSF CAREER Award in 2009.
UCSD Center for Dark Silicon
I direct the UCSD Center for Dark Silicon, which is dedicated to maximizing the amount of computation we can get out of a single square centimeter of silicon. Dark Silicon refers to factors that prevent us from using this resource at its full potential. There are three causes to dark silicon: a) power limitations because of poor CMOS scaling, b) overly large software engineering costs for parallelizing programs for multicore chips, and c) lack of parallel application domains.
My research attacks each of these problems by 1) reinventing processor design to make use of dark silicon, 2) utilizing existing cores better through better parallel software engineering tools and 3) finding new parallel application classes to put cores to work:
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Recent News
| Aug 2011 | GreenDroid QsCores paper accepted into MICRO! Congrats, Ganesh! | ||||||||||||||||||||
| June 2011 | NSF funds my proposal to support prototyping efforts! | ||||||||||||||||||||
| June 2011 | OOPSLA paper accepted! Congrats to DJ, Sat, and Chris! | ||||||||||||||||||||
| May 2011 | FPL paper accepted! Congrats to Jack and Manish! | ||||||||||||||||||||
| May 2011 | Our student, Dr. Ganesh Venkatesh, successfully defends his thesis against 5 UC professors! Ganesh will be joining Intel Research. | ||||||||||||||||||||
| April 2011 | GreenDroid featured on front page of Technology Review, and then slashdot.org. | ||||||||||||||||||||
| April 2011 | GreenDroid IEEE Micro article, The GreenDroid Mobile Application Processor: An Architecture for Silicon's Dark Future now available! | ||||||||||||||||||||
| April 2011 | Kremlin wins best Computer Science & Engineering poster (out of 40 posters!) at the Jacobs School of Engineering Research Expo! | ||||||||||||||||||||
| April 2011 | Invited talk on Conservation Cores and GreenDroid at LCTES! | ||||||||||||||||||||
| March 2011 | Parkour paper accepted into HOTPAR. Awesome work DJ! | ||||||||||||||||||||
| March 2011 | C-cores for FPGAs paper accepted into FCCM. Way to go Manish! | ||||||||||||||||||||
| Feb 2011 | Kremlin paper accepted into PLDI! | ||||||||||||||||||||
| Feb 2011 | Kremlin wins best student poster in PPoPP 2011! | ||||||||||||||||||||
| Nov 2010 | UCSD ACM Programming Team, which I coach, invited to Worlds in Egypt! | ||||||||||||||||||||
| Nov 2010 | HPCA paper on ECOcores (cores with Extreme CISC Operators) accepted. | ||||||||||||||||||||
| Oct 2010 | NSF funds my lab for $376K to attack issues in multicore programmability! | ||||||||||||||||||||
| Sept 2010 | Dr. Swanson and I have minted our first PhD student: Dr Jack Sampson! Jack will be continuing with us as a postdoc so he can shephard some of his pending papers out to the presses! | ||||||||||||||||||||
| Aug 2010 | Our student, Nathan Goulding, gives an outstanding talk on the GreenDroid work at HOTCHIPS! We were the only academic talk in the entire conference. We got coverage in the Register.co.uk, EE Times, IEEE Spectrum and others:
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| May 2010 | HOTCHIPS paper on our C-core-based chip accepted: GreenDroid: A Mobile Application Processor for a Future of Dark Silicon. | ||||||||||||||||||||
| March 2010 | Our student, Jack Sampson, gives an awesome talk on the Conservation Cores paper at ASPLOS! | ||||||||||||||||||||
| March 2010 | Our paper, Bridging the Parallelization Gap: Automating Parallelism Discovery and Planning,
was accepted into HOTPAR 2010. | ||||||||||||||||||||
| Jan 2010 | Conservation Cores camera ready version ready. If you read one architecture paper this year, read this ASPLOS 2010 Paper. | ||||||||||||||||||||
| Nov 2009 | We just released The San Diego Vision Benchmark Suite, a benchmark for the vision application domain, written in MATLAB and clean C. It's available at parallel.ucsd.edu/vision. | ||||||||||||||||||||
| Nov 2009 | Our paper, Conservation Cores: Reducing the Energy of Mature Computations, was accepted into ASPLOS 2010. | ||||||||||||||||||||
| Oct 2009 | My student, Sravanthi Kota Venkata, presents our IISWC paper on the San Diego Vision Benchmark Suite in Austin, TX. | ||||||||||||||||||||
| July 2009 | Successfully passed the FAA written test and landed an airplane four times at Long Beach Airport (LGB)! | ||||||||||||||||||||
| June 2009 | National Science Foundation CAREER Award: Energy-Efficient Parallel Architectures for Computer Vision. |
Ideal Students for my Research Group
The kinds of students that will succeed best in my group are those who love to build agressive but elegant systems and tune their performance -- compilers, graphics renderers, simulators, computers, dynamic translation emulators, operating systems, boards or even chips. They like coding, have written a lot of it, and know how to write solid, elegant code (ala Writing Solid Code or The Pragmatic Programmer), and don't mind telling others how to do it -- and maybe have worked at companies on software systems or chip design. They tend to have lots of little side projects and experiments that they have done outside of class. They might enjoy reverse-engineering things as well.
Collaborations
My collaborators here at UCSD include Steven Swanson, Dean Tullsen, Yoav Freund, Serge Belongie, CK Cheng, and the members of Calit2.
I advise or co-advise a group of fantastic graduate students and staff members; including:
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Veterans of my group include:
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Teaching
| Spring | 2012 | CSE 141: Introduction to Computer Architecture |
| Spring | 2012 | CSE 141L: Design and Implement Your Own Processor |
| Winter | 2012 | CSE 240B: Parallel Computer Architecture <----- PC |
| Fall | 2011 | CSE 291: Smartphone Processor Design |
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In this class, we will study the design decisions in multicore mobile application processors for Android and other smartphones.
Mobile applications processors are the new centroid of processor design and have a new set of interesting design constraints. In addition
to course reading, the majority of the class will be spent on a class project that extends academic research in this area.
Requirements: one or more of the following:
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| Spring | 2011 | CSE 141: Introduction to Computer Architecture |
| Spring | 2011 | CSE 141L: Design and Implement Your Own Processor |
| Winter | 2011 | CSE 240B: Parallel Computer Architecture |
| Fall | 2010 | CSE 240A: Principles of Computer Architecture |
| Spring | 2010 | CSE 141: Introduction to Computer Architecture |
| Spring | 2010 | CSE 141L: Design and Implement Your Own Processor |
Tabulature of courses taught:
| YEAR | WINTER | SPRING | FALL |
|---|---|---|---|
| 2006 | N/A | 240B | 240A |
| 2007 | 141, 141L | 291 | |
| 2008 | 240B | 141, 141L | 141, 141L |
| 2009 | 240A | 148 | 291 |
| 2010 | 240B | 141, 141L | 240A |
| 2011 | 240B | 141, 141L | 291 |
| 2012 | 240B | 141, 141L | 141, 141L |
| 2013 | 240A | 240B | 291 |
Program Committees
| ISCA | 2007 |
| NOCS | 2009, 2010, 2011, 2012 |
| MICRO | 2010 |
| IPDPS | 2010 |
| CASES | 2011, 2012 |
| FPT | 2011 |
| HOTI | 2011 |
| PPoPP ERC | 2012 |
| PACT | 2012 |
| IGCC | 2012 |
| DaSi | 2012 (Also: Organizing Committee) |
Local Arrangements Chair for ISCA 2007 (San Diego Zoo Trip)
Programming Team
I am the coach for the 2011 UCSD ACM Programming Team.
I was the coach for the 2010 UCSD ACM Programming Team, which placed second
in Southern California, and competed in the ACM Worlds in Orlando! (
I also coached in 2009, 2007 and 2006, and ran the local UCSD programming contests those years as well.
MIT Raw Processor
As one of the lead students in the
MIT Raw project, I led the design and implementation
of the Raw microprocessor, which targeted the leading VLSI technology of the time.
I also contributed heavily to almost all of the software systems that we built to support the
microprocessor. Raw was one of the earliest fabricated multicore processors, with 16 cores on a single die, back in 2002. The purpose of Raw was to demonstrate architectural solutions to scalability problems in modern day microprocessors. The Raw architecture exposes the transistor resources of VLSI chips through the tile abstraction, the pin resources through the I/O port abstraction, and the wiring resources through on-chip networks. Raw was commercialized into the Tilera TILE64 architecture.
Because the Raw architecture exposed the on-chip resources more effectively than existing sequential architectures (for instance the P6 micro-architecture, the basis of the Pentium-M), Raw was able to outperform Intel desktop processors, implemented with better process technology, across a variety of applications.
One of the key ideas that came out of the Raw research was the formulation of the Scalar Operand Network (SON), a unique class of sub-nanosecond network responsible for routing operands between functional units and memories in a distributed microprocessor.
My team implemented the 16-tile Raw microprocessor, shown to the upper-left, in IBM's SA-27E 180 nm 6-layer Cu ASIC process. The 18.2 mm x 18.2 mm chip was, at least at the time, the largest design that the IBM ASIC division had targeted for SA-27E. Each tile contains computing power equivalent to a single-issue pipelined processor. We taped out the chip in August '02, and received prototypes back in late October '02. The motherboard was assembled January '03. A supercomputer prototype, based on 4-chip boards, that scaled to 64 Raw chips (1024-issue) was constructed.
More pictures are available here.
Downloads
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The San Diego Vision Benchmark Suite, a benchmark for the vision application domain, written in MATLAB and clean C.
It's available at cseweb.ucsd.edu/~mbtaylor/vision. |
Selected Publications (Click to view by topic)
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Technology Policy Advocacy
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Testimony regarding Massachusetts House Bill No. 2743, entitled An Act to Improve Broadband and Internet Security, at Massachusetts Joint Committee On Criminal Justice on April 2, 2003. This testimony was referenced by Ed Felton's Freedom to Tinker website and discussed in a law journal article: "Super-DMCA" Statutes: Putting Hollywood in Charge of Internet Business, Matthew A. Verga, Wake Forest Intellectual Property Law Journal 104, May 2004. |
Software
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A tool for deionization, which enables
application embedding and improved benchmark precision.
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Miscellaneous
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For your (and my) entertainment...
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Mailing Address
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Prof. Michael B. Taylor Dept. of Computer Science and Engineering University of California, San Diego 9500 Gilman Drive EBU 3b-3202 MC 0404 La Jolla, CA 92093-0404 |