Research Directions

We plan to continue, and further extend our work of system on chip in terms of circuit analysis and floorplanning including field programmable components, interconnect architectures, and adaptive data path modules. For circuit analysis, we research efficient methods to model and check the signal integrity of huge networks. During this process, we establish circuit design guidelines that minimize crosstalk and power-supply fluctuations, while at the same time balance delay and the amount of ringing.

Floorplan optimization is considered to be one pivotal step in the deep submicron design methodology. The research on this topic will provide very high return toward achieving parity between technology capability and design productivity. We propose to study interconnect architecture, performance-driven layout planning, and adaptive data path modules, which constitute critical ingredients of system on chip designs.

Sample Publications

Circuit Simulation

C.K. Cheng, J. Lillis, S. Lin, N. Chang, Interconnect Analysis and Synthesis, John-Wiley, 2000.

Z. Qin and C.K. Cheng, " Realizable Parasitic Reduction Using Generalized Y-Delta Transformation, " ACM/IEEE Design Automation Conference, pp. 220-225, June 2003.

Floorplanning

S. Chen and C.K. Cheng, "Tutorial on VLSI Partitioning," VLSI Design, pp. 175-218, vol. 11, no. 3, 2000.

P.N. Guo, T. Takahashi, C.K. Cheng, and T. Yoshimura, "Floorplanning using a Tree Representation," IEEE Trans. on CAD, pp. 281-289, Feb. 2001.

C.K. Cheng and A. Kahng, Rapid Prototyping Systems, Wiley Encyclopedia of Electrical and Electronics Engineering, by J. G. Webster, vol. 18, pp. 234-242, 1999.

Interconnect Architecture

E.Y. Cheng, F. Zhou, B. Yao, C.K. Cheng, and R. Graham, "Balancing the Interconnect Topology for Arrays of Processors between Cost and Power," to IEEE Int. Conf on Computer Design, pp. 30-35, Sept. 2002.

H. Chen, B. Yao, F. Zhou, and C.K. Cheng, "Physical Planning of On-Chip Interconnect Architectures," IEEE Int. Conf on Computer Design, pp. 180-186, Sept. 2002.

Placement and Partitioning

C.K. Cheng and E.S. Kuh, " Module Placement Based on Resistive Network Optimization, " IEEE Trans. on Computer-Aided Design, vol. CAD-3, pp. 218-225, July 1984.

C.K. Cheng and T.C. Hu, " Ancestor Tree for Arbitrary Multi-Terminal Cut Functions, " Integer Programming/Combinatorial Optimization Conf., Univ. of Waterloo, pp. 115-127, May 1990.

C.K. Cheng and T.C. Hu, " Maximum Concurrent Flow and Minimum Ratio Cut, " Algorithmica, vol. 8, pp. 233-249, 1992.

C. Yeh, C. K. Cheng and T. T. Lin, " Circuit Clustering Using A Stochastic Flow Injection Method, " IEEE Trans. on CAD, pp. 154-162, Feb. 1995.

L.T. Liu, M.T. Kuo, C.K. Cheng, and T.C. Hu, " A Replication Cut for Two-Way Partitioning, " IEEE Trans. on CAD, pp. 623-630, May 1995.