1. Improved IC Design Floorplan Generation using Ceiling and Floor Contours on an O-Tree Structure filed on 6/19/99, by CK Cheng and Pei-Ning Guo, 6,282,694, 8/28/01.
2. Interconnect Delay Driven Placement and Routing of an Integrated Circuit Design, filed on 4/8/99, by CK Cheng and So-Zen Yao, 6,327,693, 12/4/01.
3. Method and Apparatus for Clock Tree Solutions Synthesis based on Design Constraints filed on 6/19/99 by CK Cheng and Jiang-Jih Chao 6,367,060, 4/2/2002.
4. Efficient Transistor Level Simulation Using Two-Stage Newton-Raphson and Multigrid Method, CK Cheng and Zhengyong Zhu, 7,555,416, 7/30/2009.