Chung-Kuan Cheng

Professor

Department of Computer Science and Engineering,

University of California, San Diego,

La Jolla, CA 92093-0404

Address for express mail:

9500 Gilman Dr., Building EBU3 Room 2130

CSE Dept., UC San Diego, La Jolla, CA 92093-0404

Email: ckcheng at ucsd dot edu, Tel: (858) 534-6184, Fax: (858) 534-7029

I am a Professor at the Department of Computer Science and Engineering and an Adjunct Professor at the Department of Electrical and Computer Engineering, the University of California, San Diego. I have served as a Senior Engineer, Chief Scientist, and Consultant at various System, Design, and Electronic Desgin Automation Companies. I got my Ph.D. from the Department of Electrical Engineering and Computer Science at the University of California, Berkeley in 1984.

Recent Photos
Star power, 2004

Annual event, 2005

Cruising in San Diego, 1/04/07

IBM EIP Award at EPEP 10/29/07
CK Cheng on 01/05/2010

Books or Chapters

C.K. Cheng and A. Kahng, Rapid Prototyping Systems, Wiley Encyclopedia of Electrical and Electronics Engineering, by J. G. Webster, vol. 18, pp. 234-242, 1999.

C.K. Cheng, J. Lillis, S. Lin, N. Chang, Interconnect Analysis and Synthesis, John-Wiley, 2000, Japanese version edited by H. Onodera, 2003, ISBN4-563-06718-0 C3005, Chinese version edited by W. Yu, 2008, ISBN978-7-302-15732-8.

C.K. Cheng, Z. Qin, and S. Tan, Symbolic Analysis and Reduction of VLSI Circuits, Springer, 2004.

Z. Feng, B. Yao, and C.K. Cheng, Floorplan Representation in VLSI, Handbook of DATA Structures and Applications, by D.P. Mehta and S. Sahni, Chapman & Hall/CRC, pp. 53-1: 53-29, 2004.

Released Packages and Report

Ratio Cut Package, 1989-1995

Ratio Cut Partitioning

RLC Reduction of Interconnect, 1999-2003

Y-Delta Transformation

Floorplanning of Blocks, 1999-2001

O-Tree Floorplanning

Y Architecture, 2002-2003

Physical Planning, Y-Architecture Yet another Y-Architecture

Surfliner, 2005

Distortionless Transmission Line

FPGA Interconnect Architecture Package, 2006-2008

FPGA Interconnect Architecture Synthesis for Power Minimization

Eye Diagram Prediction Package, 2006-2008

Eye Diagram Prediction with Asymmetric Transitions

Interconnect Architecture Topology Synthesis, 2006-2008

Topology Synthesis for Many Core Systems such as Supercomputers

Honors and Awards

NCR Best Teaching Award, School of Engineering, University of California, San Diego, 1991.
IEEE Circuits and Systems Society, CAD Transactions Best Paper Awards, 1997, 2002.
IEEE Fellow, 2000.
IBM Faculty Awards, 2004, 2006, 2007.
Honorary Appointment as a Guest Professor of the Department of Computer Science & Technology, Tsinghua University, 2002-2008.

Services

Program Co-Chair, Int. Conf. on ASIC, ASICON, Oct. 2003.
Program Co-Chair, IEEE ASPDAC 2004.
Tutorial Co-Chair, IEEE ASPDAC 2005.
President 2003-2005, San Diego Chinese American Science and Engineering Association.
Tutorial Co-Chair, IEEE ASPDAC 2006.
One Day Tutorial Co-Organizer, ACM/IEEE DAC 2006.
Co-Chair, EDA Program, ICCCAS 2009.
General Chair, ACM/IEEE SLIP 2009.
UCSD Academic Senate Committee on Diversity and Equity (Member, Vice Chair, Chair, 2008-2011)
- Annual Report on Diversity and Equity, 05/25/2010
- Annual Report Presentation, pdf, ppt file, 05/25/2010