The low power and high speed of flash memory make it popular in a wide range of
applications from the hand held to the data center. In all these applications,
system power loss poses a serious danger to data in flash devices. If the flash
memory device loses power during a program or erase operation, the corruption
of meta data may cause the whole device become inoperable. To better
understand the behavior of flash memory when power fails, we use custom-built platform
and directly measure the
errors that cutting power to flash chips during program or erase operations can
cause in this project.
Hung-Wei Tseng, Laura M. Grupp, Adrian M. Caulfield, Joel Coburn, Eitan
Yaakobi, Paul H. Siegel, Jack K. Wolf and Steven Swanson. Characterizing
flash memory for power failure. Flash Memory Summit, August 2010.
Most computers today implement the Von Neumann architecture that consists of
processors and main memory. In addition to the notorious "von Neumann"
bottleneck, this model also incurs lots of redundant computation and memory
accesses due to the artifical execution order and limited registers.
Data-Trigger Thread proposes a smooth transition to data-flow execution
model on top of conventional processors. Unlike the traditional models, we
initiate a thread on a change to a memory location. This model enables
increased parallelism and the elimination of redundant, unnecessary
computation.
Hung-Wei Tseng and Dean M. Tullsen.
Data-Triggered
Threads: Eliminating Redundant Computation. In Proceedings of 17th International Symposium on High Performance Computer
Architecture (HPCA-17), page 181-192, February, 2011. Nominated for Best Student Paper!
