FINAL PROGRAM

November 12, 1998, Thursday

6:00 pm - 7:00 pm Workshop Registration
7:00 pm - 10.00 pm Reception

Welcoming Remarks: Robert Conn, Dean, Jacobs School of Engineering, UC San Diego

November 13, 1998, Friday

7:30-7:45 Breakfast
7:45 - 8:00 Welcoming Remarks

Sujit Dey, General Chair

Alex Orailoglu, Program Chair

8:00 - 9:15 SESSION 1 VERIFICATION OF MICROPROCESSOR DESIGNS
Chair: R. Bergamaschi, IBM
1. High-Level Test Generation for Design Verification of Pipelined Microprocessors
  D. Van Campenhout, T. Mudge, J.P. Hayes, University of Michigan
2. Encoding Techniques for Symbolic Data Values in the Verification of Pipelined Microprocessors by Correspondence Checking
  M.N. Velev, R.E. Bryant, CMU
3. False Timing Paths and Environment Modeling: Experiments on PowerPC^TM Microprocessors
  R. Raimi, Motorola, J. Abraham, University of Texas, Austin
9:30 - 10:45 SESSION 2 HARDWARE/SOFTWARE CO-VALIDATION
Chair: G. Bunza, Synopsys
1. A Framework for High-Level Performance Validation of Embedded HW/SW Systems
  D. Ziegenbein, R. Ernst, TU Braunschweig
2. Multi-phase Validation of Hardware/Software Interfaces based on Generated Simulation Models
  M. O'Nils, A. Jantsch, Royal Institute of Technology, Sweden
3. Validation of Interface Protocols Using Grammar-based Models
  J. Öberg, A. Jantsch, A. Hemani, Royal Institute of Technology, Sweden
11:00 - 12:00 SESSION 3 FORMAL METHODS FOR HIGH-LEVEL DESIGNS AND EMBEDDED SYSTEMS
Chair: J.P. Hayes, Univ. of Michigan
1. A New Extended Finite State Machine (EFSM) Model and Its Application to Functional Vector Generation
  R. Chung-Yang Huang, K-T Cheng, UCSB
2. Property-dependent Modular Model Checking Application to VHDL with computational results
  F. Rahim, University of Paris (VI)
3. Verifying High-Level Synthesis Results Using a Partial Order Based Model
  C. Hansen, U. of Karlsruhe, F. Nascimento, W. Rosenstiel, U. of Tuebingen
4. How to Evaluate the Performance of an Embedded System through its Formal Specification.
  V. Carchiolo, M. Malgeri, G. Mangioni, Universita di Catania
12:00 - 1:30 LUNCH AND DISCUSSION
1:30 - 2:45 SESSION 4 VERIFICATION OF APPLICATION-SPECIFIC PROCESSORS
Chair: C. Kumbasar, Cadence
1. Efficient functional validation of system-level loop transformations for multi-media applications
  M. Cupak, F. Catthoor, H. De Man, IMEC
2. Algorithm Level Verification of Arithmetic Intensive Application Specific Hardware Designs for Computation Accuracy
  S.A. Wadekar, A.C. Parker, USC
3. Test Methodology of a Very Large Instruction Word Processor
  A. Fortas, R.J.W.T. Tangelder and H.G. Kerkhoff, University of Twente
3:00 - 3:45 SESSION 5 HIGH-LEVEL TESTABILITY & FAULT MODELS
Chair: S. Davidson, SUN
1. Study of Correlation of Testability Aspects of HDL Code and Resulting Structural Implementations
  P. Thaker,Hughes Network Systems, M. Zaghloul, George Washington University, M. Amin, Synopsys
2. Vector-Based Functional Fault Models for Delay Faults
  Irith Pomeranz, Sudhakar M. Reddy, U. of Iowa
3. Datapath testability improvement through ad hoc controller modifications
  M. L. Flottes, R. Pires, B. Rouzeyre, LIRMM
4:00 - 5:30 SESSION 6 PANEL: INDUSTRIAL DESIGNS: WHAT VERIFICATION/VALIDATION METHODOLOGIES CAN BE USED ?

Moderator: R. Raina, Motorola

J. Abraham, Univ. of Texas at Austin
M. Bershteyn, Quickturn
J. Kukula, Synopsys
M. Srivas SRI
C. Wilson, HAL/Fujitsu

5:45 - 10:00 CRUISE & DINNER

November 14, 1998, Saturday

7:30-8:00 Breakfast
8:00 - 9:40 SESSION 7 ISSUES IN TESTING CORE-BASED SYSTEM CHIPS
Chair: J. Rajski, Mentor Graphics
1. Criteria of Performance Verification and Test for Core-Based LSIs
  H. Date, ISIT/Kyushu, H. Tomiyama, H. Yasuura, Kyushu University
2. Test Vector Compression/Decompression for Systems-on-a-Chip Using Statistical Coding
  A. Jas, J.G. Dastidar, N.A. Touba, University of Texas, Austin
3. A Distributed BIST Manager for Hierarchical System Test and Diagnosis
  A. Benso, S. Chiusano, P. Prinetto, Politecnico di Torino, Y. Zorian, LogicVision
4. Intellectual Property Protection using Watermarking Partial Scan Chains for Sequential Logic Test Generation
  D. Kirovski, M. Potkonjak, UCLA
9:50 - 10:50 SESSION 8 NOVEL APPROACHES FOR HIGH-QUALITY SYSTEMS
Chair: J. Jess, Eindhoven University of Technology
1. A Pseudo-Random Approach to Verify Error and Interrupt Handling in a Corelogic Chipset
  C-H Chien, L. Noack, D. Katz, B. Lineback, T. Moore, Compaq
2. Fault Location in FPGA-Based Reconfigurable Systems
  S. Mitra, P.P. Shirvani, E.J. McCluskey, Stanford
3. Heterogeneous Built-in Resiliency of Application Specific Programmable Processors
  K. Kim, Samsung Electronics, R. Karri, Polytechnic University, M. Potkonjak, UCLA
11:00 - 12:15 SESSION 9 VALIDATION OF COMMUNICATION INTERFACES AND SYSTEMS
Chair: Prab Varma, Veritable
1. Formal Specification and Verification of Communication-systems for Designing in VHDL
  O. Drogehorn, O. Terhorst, H-D Hummer, W. Geisselhardt, Gerhard-Mercator-University, Duisburg
2. High-Level Modeling of Communication in Embedded Real-Time Systems
  D. Ramanathan, Synopsys, A. Dasdan, University of Illinois, R.K. Gupta, University of California, Irvine
3. A high-level modeling method of communication systems using PVM
  S. Ishihara, A. Takahara, NTT
12:15 - 1:30 LUNCH AND DISCUSSION
1:30 - 3:00 SESSION 10 DISCUSSION PANEL ON HOT TOPICS IN TEST & VERIFICATION

Moderator: P. Marwedel, University of Dortmund

3:15 - 4:55 SESSION 11 VALIDATION AND TEST OF MICROPROCESSORS
Chair: P. Vishakantaiah, Intel
1. High-Level Test Generation Experiments on PowerPC^TM Microprocessors
  R. Raina, Motorola
2. Micro Architecture Coverage Directed Generation of Test Programs
  S. Ur, Y. Yadin, IBM Haifa
3. Validation of Microprocessors Using Real World Applications
  Y-S Chang, S-J Lee, C-M Kyung, I-C Park, KAIST
4. Developing an Architecture Validation Suite: Application to the PowerPC Architecture
  L. Fournier, A. Koyfman, M. Levinger, IBM Haifa