FINAL PROGRAM

Thursday, November 14, 1996

• 6:00 pm - 7:00 pm Workshop Registration
• 7:00 pm - 9:00 pm Reception

Friday, November 15, 1996

• 8:05-8:15 -- Welcoming Remarks --
• 8:15-9:15 --SESSION 1A-- Verification & Test of Processors & Embedded Systems
  Chair: J. Patel, Univ. of Illinois, Urbana-Champaign
  1. Symbolic Verification of Instruction-Set Processors
     D. Galter - Nortel Tech., F. Mavaddat - Univ. of Waterloo,
  2. STAR-DUST: Hierarchical Test of Embedded Processors by Self-Test Programs
     U. Bieker, P. Marwedel - Univ. of Dortmund,
     M. Kaibel, W. Geisselhardt - Univ. of Duisburg,
  3. High Level DFT for Hardware/Software Co-Testing
     H.P.E. Vranken, M.P.J. Steven - Eindhoven Univ. of Tech,
     M.T.M. Segers - Philips Semiconductors
• 9:45-10:45 --SESSION 1B-- Testing Core-based Designs
  Chair: B. Koenemann, LogicVision
  1. Partial Isolation Rings for Testing Embedded Cores
     N.A. Touba - Univ. of Texas at Austin,
     E.J. McCluskey - Stanford Univ.,
  2. A Framework for Testing Core Based Designs
     K. Lai and C. Papachristou - Case Western Reserve Univ.
  3. Towards A Common Core Test Specifications
     W-Y. Koe - Fujitsu Microelectronics Inc.,
     C. Mallipeddi - Cadence Design Systems,
     T. Yoshimori - Toshiba Corp.
• 11:15-12:15 --SESSION 1C-- Hardware-Software Co-Validation
  Chair: A. A. Jerraya, TIMA/INPG
  1. HW/SW Co-Validation of Behavioral Descriptions of Data Processing Systems
     M. Deegener and S.A. Huss - Tech Univ of Darmstadt,
  2. High-Level Validation Strategies for Broadband Network Components: A Case Study on Charging Algorithm Design
     G. Post, A. Mueller, H. Meyr - Aachen Univ. of Tech,
  3. Rapid Architectural Design and Validation Using Program-Driven Simulations
     A. Chien, A. Dasdan, R.K. Gupta, B. Zhang - Univ. of Illinois, Urbana-Champaign,
• 12:30-2:00 --Lunch--
• 2:00-3:15 --SESSION 1D-- Simulation-based and Formal Validation and Correction
  Chair: R. Vemuri - Univ. of Cincinnati
  1. A VHDL Test Bench Generator for Functional Implementation Verification
     D. Jiang, T-Y. Yen, J. Wang, T-C. Lin - Quickturn Design Systems
  2. AQUILA: A Hybrid Approach to Sequential Equivalence Checking
     S-Y. Huang, K-C. Chen - Fujitsu Labs of America,
     K-T. Cheng - Univ. of California, Santa Barbara
  3. A Methodology for the Design of Guaranteed Correct and Efficient Digital Systems
     P.F.A. Middelhoek, C. Huijs, G.E. Mekenkamp, E.W. Prangsma, E. Engels, and J. Hofstede - Univ. of Twente,
  4. Combining Formal Verification with VLSI Design
     A. Chavan, J.D. Kim, B. Min, S-K. Chin - Syracuse Univ.,
     J-Y.J. Lu - National Semiconductor Corp.,
  5. A New Design Methodology Tolerant Against Design Errors
     P. Kindsmueller, W. Stechele, M.R. Movahedin - Tech. Univ. of Munich, Germany
• 3:30-5:00 --SESSION 1E-- Considering Testability During High Level Design
  Chair: J. Rajski, Mentor Graphics
  1. A testability analysis for driving architectural synthesis
     M.L. Flottes, R. Pires, B. Rouzeyre - LIRMM
  2. High-Level Synthesis of Self-Testable Circuits Through Fast Behavioral Fault Simulation
     I.G. Harris and A. Orailoglu - Univ. of California, San Diego,
  3. Global Test Scheduling and Control in a HL-SFT Environment
     M. Marzouki, W. Maroufi - TIMA-CMP,
     V. Castro Alves, A. Ribeiro Antunes - LPC-COPPE/UFRJ, Brazil
  4. Early Mode Design-for-Test Synthesis in a Production Environment
     V. Chickermane, K. Zarrineh - IBM Microelectronics
• 6:30-8:00 --Dinner--
• 8:00-9:30 --SESSION 1F-- Panel: Validation and Test of Core-Based Systems
  Moderator: Yervant Zorian, Lucent Bell Labs
  Panelists:
  • T. Anderson, Virtual Chips
  • G. Bunza, Eagle Design Automation
  • M. Meyer, Alta Group of Cadence
  • T. Nukiyama, NEC Corp
  • S. Soman, LSI Logic

Saturday, November 16, 1996

• 8:00-9:00 --SESSION 2A-- Reducing the Complexity of Validation
  Chair: K. McMillan, Cadence Berkeley Labs
  1. SpotLight: Best-First Search of FSM State Space
     C. Han Yang, David L. Dill - Stanford Univ
  2. VHDL Slices for High Level Design Validation
     M. Iwaihara, S. Ichinose, M. Nomura, H. Yasuura - Kyushu Univ
  3. A VHDL-based hierarchical, highly flexible and extendable Test Bench Approach
     W. Ecker, M. Bauer - Siemens Corporate R&D,
• 9:30-10:30 --SESSION 2B-- Specification & Modeling Facilitating Validation
  Chair: W. Rosenstiel - Tuebingen Univ.
  1. Higher Level Specification: A Constraint-Based System in Practice
     K.D. Jones, J.P. Privitera, T.J. Sheffler - Rambus Inc,
  2. A High-Level Language for Programming Complex Temporal Behaviors and its Application to Design Validation
     C-T Chou, M. Fujita - Fujitsu Lab. of America, Santa Clara, J-L Huang - Univ. of California, Santa Barbara,
  3. Modeling micro-controller peripherals for high-level co-simulation and synthesis
     P. Giusto - Magneti Marelli,
     L. Lavagno, C. Sansoe - Politecnico di Torino,
     A. Sangiovanni-Vincentelli - Univ. of California, Berkeley,
• 11:00-12:00 --SESSION 2C-- Considering Validation During High Level Synthesis
  Chair: R. Bergamaschi - IBM
  1. Re-use of Test Vectors for High Level Verification
     C. Hansen, A. Kunzmann - Univ. of Karlsruhe(FZI),
     W. Rosenstiel - FZI and Univ. of Tubingen,
  2. Correct Reuse of Complex Design Units During High Level Synthesis: Verification Issues
     J. Dushina, A.A. Jerraya, D. Borrione - TIMA,
  3. Validation of Synthesized Register-Transfer Level Designs Using Simulation and Formal Verification
     N. Narasimhan, R. Kalyanaraman, R. Vemuri - Univ. of Cincinatti,
• 12:00-1:30 Lunch
• 1:30-2:30 --SESSION 2D-- High Level Simulation & Testing Methodologies
  Chair: K. Wagner, Synopsys
  1. A Testing Methodology for VHDL Based High-Level Designs
     G. Buonanno, F. Ferrandi, F. Fummi, D. Sciuto - Politecnico di Milano,
  2. Including Testability in a High-Level Synthesis Environment
     A.R. Antunes, V.C. Alves, A. Mesquita - LPC-COPPE/UFRJ,
     M. Marzouki - TIMA
  3. High-Level Test Generation for Clock Regenerators in PowerPC Microprocesors
     R. Raina, C. Njinda, R. Bailey, B. Long - Motorola,
     C. Beh, B. Molyneaux - IBM Corp.,
  4. AHDL-Based Analog Behavioral Fault Modeling and Simulation
     W.H. Kao - Cadence Design Systems
     R. Voorakaranam, A. Chatterjee - Georgia Tech
• 2:45-4:15 --SESSION 2E-- Panel: High Level Design Validation: In Practice
  Moderator: Raj Raina, Motorola
  Panelists:
  • W. Anderson, DEC
  • R. Bergamaschi, IBM
  • P. Jain, CAE Plus
  • J-P. Masbou, Intel
  • B. West, Schlumberger Tech