Call for papers(
pdf)
Steering Committee
Sujit Dey, UC San Diego
Alex Orailoglu, UC San Diego
Prab Varma, Veritable, Inc.
Organizing Committee
General Chair
Vijay Nagasamy, Ciena |
Program Chair
Masahiro Fujita, U Tokyo |
Vice Program Chair
Wolfgang Rosenstiel, Tuebingen U |
Past Chair
Rajesh Gupta, UC Irvine |
Finance Chair
Ramesh Karri, Polytechnic U. |
Panels Chair
Alan Hu, U. British Columbia |
Publicity Chair
Bernard Courtois, TIMA |
Publications Chair
Ahmed Jerraya, TIMA |
Local Arrangements Chair
Sandeep Bhatia, Cadence |
European Liaison
Peter Marwedel, Dortmund U. |
Asian Liaison
Hiroto Yasuura, Kyushu University |
Industry Liaison
Raj Raina, Motorola |
Program Committee
M. Abadir, Motorola
J. Abraham, UT Austin
F. Balarin, Cadence Berkeley L
K-T. Cheng, UC Santa Barbara
L. Claesen, KU.Leuven
H. Date, ISIT/KYUSHU
H. Eveking, TU Darmstadt
F. Fallah, Fujitsu Labs US
R. Hale, SRI Cambridge
K. Hamaguchi, Osaka U
J. Hayes, U Michigan
Y. Hoskote, Intel
J. Jess, Eindhoven U
R. Jones, Intel
L. Lavagno, U di Udine
E. McCluskey, Stanford U
Y. Matsunaga, Kyusyu U
I. Pomeranz, U. Iowa
M. Potkonjak, UC Los Angeles
P. Prinetto, Politecnico di Torino
S. Rajan, Fujitsu Labs US
B. Rouzeyre, LIRMM
D. Saab, Case Western Reserve U
P. Schaumont, IMEC
M. Srivas, RealChip
A. Takahara, NTT
Y. Zorian, LogicVision
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HLDVT'2001 is the sixth in a series of annual workshops designed to bring together a community of researchers in the areas of microelectronic design, verification, and test. The workshop revolves around a common theme of addressing the integration of multiple functions on-chip at higher levels of design abstraction, and the techniques and methodologies for validating such systems. The workshop provides an informal forum for discussion of substantive issues that cut across diverse areas in system-level design. Major topics include, but are not limited to, the following:
High Level Design Validation
High Level Design Error Modeling
High Level Test Bench Generation
Testing Core Based Designs
Hardware/Software Co-Testing
Simulation-Based Verification
Emulation and Prototyping
Error Models and Verification Test
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Hardware/Software Co-Validation
High Level DFT/Synthesis for Test
High Level ATPG/Fault Simulation
Validation of Microprocessors
Design Error Debug & Diagnosis
Formal Verification Methods
On-Chip Software Testing
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The Program Committee invites authors to submit an extended summary comprising of no more than a 1000 words, describing original, unpublished recent work. Clearly describe the nature of the work, explain its significance, highlight novel features, and describe its current status. On the title page, please indicate: title, name and affiliations of all authors, and the topic category. Also identify a contact author and provide complete mailing address, phone number, fax number and an e-mail address. Panel proposals are also invited. All submissions must be made electronically via E-mail in PDF or Postscript format.Submissions are due no later than June 30, 2001.
| Submit all papers & proposals to: |
For general information, contact: |
Masahiro Fujita, Program Chair
Dept. of Electronic Engineering
University of Tokyo
7-3-1, Hongo, Bunkyo-ku
Tokyo 113-8656, Japan
Email: fujita@ee.t.u-tokyo.ac.jp
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Vijay Nagasamy, General Chair
Ciena Corporation
47100 Bayside Parkway
Fremont, CA 94538
T: 510-661-5512, F: 510-490-7705
E-mail: vnagasamy@ciena.com
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Authors will be notified of the disposition of their papers by August 17, 2001. The submission of a proposal will be considered evidence that upon acceptance, the author(s) will present their paper at the workshop. Authors of accepted papers would have the option of including a camera-ready copy of their manuscript in the formal workshop proceedings published by IEEE Computer Society press. The final manuscript will be due Sept 7, 2001.
HLDVT'2001 is sponsored by the IEEE Computer Society Test Technology
Technical Council and the IEEE Computer Society Design Automation
Technical Committee.
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