IEEE International High Level Design
Validation and Test Workshop 2001
November 7-9, 2001, Monterey Hilton, Monterey, California

ADVANCE PROGRAM

Wednesday, November 7

  • 6:00-7:30pm Registration

Thursday, November 8

  • 8:30-8:45am Welcoming Remarks
  • 8:45-10:15am SESSION 1: Design validation of microprocessors
    Session Chair: Yatin Hoskote, Intel
    1. Relating Buffer-oriented Microarchitecture Validation to High-Level Pipeline Functionality
      Noppanunt Utamaphethai, R. D. (Shawn) Blanton, John P. Shen
      Carnegie Mellon University, Pittsburgh, PA
    2. Automatic Validation of Pipeline Specifications
      Prabhat Mishra, Nikil Dutt, Alex Nicolau
      University of California at Irvine, Irvine, CA
    3. Automatic Test Generation for Micro-architectural Verification of Configurable Microprocessor Cores and its Extensions
      Nupur Bhattacharyya, Albert Wang
      Tensilica Inc., Santa Clara, CA
       
  • 10:15-10:45am Break
     
  • 10:45-12:15pm SESSION 2: Techniques for high level design validation and test
    Session Chair: Rajarshi Mukherjee, Fujitsu Laboratories of America, CA
    1. Integrating Perl, Tcl and C++ into Simulation-Based ASIC Test Environments
      Michael D. McKinney
      Texas Instruments Inc., Dallas, TX
    2. Symbolic Simulation Heuristics for High-Level Design Descriptions with Uninterpreted Functions
      Kiyoharu Hamaguchi
      Osaka University, Osaka, Japan
    3. Estimating the Relative Single Stuck-at Fault Coverage of Test Sets for a Combinational Logic Block from its Functional Description
      Irith Pomeranz*, Sudhakar M. Reddy**
      * Purdue University, W. Lafayette, IN
      ** University of Iowa, Iowa City, IA
       
  • 12:15-1:30pm Lunch
     
  • 1:30-3:00pm SESSION 3: Invited Session: State-of-the-art Formal Verification Techniques
    Session Chair:  Masahiro Fujita, Univ. of Tokyo
    1. Practical Use of Sequential ATPG for Model Checking: Going the Extra Mile Does Pay Off
      Michael S. Hsiao*, Jawahar Jain,**
      *Virginia Tech
      **Fujitsu Laboratories of America
    2. Advanced SAT techniques
      Sharad Malik, Lintao Zhang
      Princeton University
    3. Symbolic Simulation Techniques - State-of-the-art and Applications
      Claudia Blank, Hans Eveking, Jens Levihn and Gerd Ritter
      Darmstadt University of Technology, Germany
       
  • 3:00-3:30pm Break
     
  • 3:30-4:30pm SESSION 4: Short Papers: High Level Verification and Analysis
    Session Chair: Hiroyuki Tomiyama, ISIT Japan
    1. A Model Checking Approach to Evaluating System Level Dynamic Power Management Policies for Embedded Systems
      Sandeep K. Shukla, Rajesh K. Gupta
      University of California at Irvine, Irvine, CA
    2. RTL Functional Verification Using Excitation and Observation Coverage
      Byeong Min, Gwan Choi
      Texas A&M University, College Station, TX
    3. Improving Test Quality Through Resource Reallocation
      Allon Adir, Eitan Marcus, Michal Rimon, Amir Voskoboynik
      IBM Research Labs in Haifa, Haifa, Israel
    4. Taylor Expansion Diagrams: A New Representation for RTL Verification
      M. Ciesielski*, P. Kalla*, Z. Zeng*, B. Rouzeyre**
      * University of Massachusetts Amherst, MA
      ** de Robotique et de Microelectronique de Montpellier, Montpellier, France
       
  • 4:30-5:30pm SESSION 5: Short Papers: High Level Timing Verification and Testing
    Session Chair: Hiroshi Nakamura, Unversity of Tokyo
    1. Fast Timed Cosimulation of HW/SW Implementation of Embedded Multiprocessor SoC Communication
      Sungjoo Yoo, Gabriela Nicolescu, Lovic Gauthier, Ahmed A. Jerraya
      TIMA/INPG, France
    2. Test Pattern Generation for Timing-Induced Functional Errors in Hardware-Sofware Systems
      Ian G. Harris
      University of Massachusetts
    3. Combining Complex Event Models and Timing Constraints
      Marek Jersak, Kai Richter, Rolf Ernst
      Technische Universitat Braunschweig, Braunschweig, Germany
    4. Formalizing Message Sequence Diagrams for Protocol Specification and Compliance Verification
      Annette Bunker, Ganesh Gopalakrishnan
      University of Utah, Salt Lake City, UT
       
  • 6:00-8:00pm Dinner
     
  • 8:30-10:00pm EVENING PANEL: Moving Beyond Verilog and VHDL: Are New Languages the Answer for Design, Validation, and Test?
    Moderator: Alan Hu, University of British Columbia

Friday, November 9

  • 8:30-10:00am SESSION 6: Verification of Real Life Designs
    Session Chair: Robert B. Jones, Intel
    1. Proving Sequential Consistency by Model Checking
      Tim Braun*, Anne Condon**, Alan J. Hu**, Kai S. Juse*, Marius Laza**,  Michael Leslie**, Rita Sharma**
      * Technical University of Darmstadt, Darmstadt, Germany
      ** University of British Columbia, Vancouver, BC, Canada
    2. Experience with Term Level Modeling and Verification of the MCORE Microprocessor Core
      Shuvendu Lahiri, Carl Pixley, Ken Albin
      Motorola, Austin, TX
    3. Formal Verification of the Pentium4 Multiplier
      Roope Kaivola, Naren Narasimhan
      Intel Corporation, Hillsboro, OR
       
  • 10:00-10:30am Break
     
  • 10:30-11:30am SESSION 7: High Level Specification and Verification
    Session Chair: Sandeep Bhatia, Cadence
    1. Exploiting High-Level Information to Scale Down Design Sizes for RTL Property Checking
      Peer Hohannsen
      SIEMENS AG, Munich, Germany
    2. Constraints Specification at Higher Levels of Abstraction
      Felice Balarin*, Jerry Burch*, Luciano Lavagno*, Yosinori Watanabe*, Robert Passerone**, Alberto Sangiovanni-Vincentelli**
      * Cadence Berkeley Laboratories, Berkeley, CA
      ** University of California at Berkeley, Berkeley, CA
    3. A Language Formalism for Verification of PowerPC Custom Memories Using Compositions of Abstract Specifications
      Jayanta Bhadra*, Andrew K. Martin*, Jacob A. Abraham**, Magdy S. Abadir*
      * Motorola Inc., Austin, TX
      ** The University of Texas at Austin, Austin, TX
       
  • 11:30-1:00pm Lunch
     
  • 1:00-2:30pm SESSION 8: High level Test Generation and Coverage Analysis
    Session Chair: Felice Balarin, Cadence Berkeley Lab
    1. On Generation of The Minimum Pattern Set for Data Path Elements in SoC Design Verification Based on Port Order Fault Model
      Chun-Yao Wang, Shing-Wu Tung, Jing-Yang Jou
      National Chiao Tung University, Hsinchu, Taiwan, R.O.C.
    2. Hardware-Software Covalidation: Fault Models and Test Generation
      Ian G. Harris
      University of Massachusetts, Amherst, MA
    3. Observability Enhanced Coverage Analysis of C programs for Functional Validation
      Farzan Fallah, Indradeep Ghosh
      Fujitsu Labs. of America, Sunnyvale, CA
       
  • 2:30-3:00pm Break
     
  • 3:00-4:30pm SESSION 9: Improved techniques for Boolean reasoning
    Session Chair: Kuang-Chien Chen, Verplex, CA
    1. Using Cutwidth to Improve Symbolic Simulation and Boolean Satisfiability
      Dong Wang*, Edmund Clarke*, Yunshan Zhu**, James Kukula**
      * Carnegie Mellon University, Pittsburgh, PA
      ** Synopsys Inc.
    2. An Enhanced Cut-points Algorithm in Formal Equivalence Verification
      Zurab Khasidashvili, John Moondanos, Daher Kaiss, Ziyad Hanna
      Intel Corp., Haifa, Israel
    3. An Analysis of ATPG and SAT algorithms for formal verification
      G. Parthasarathe*, Chung-Yang Huang**, Kwang-Ting Cheng*
      * University of California at Santa Barbara, Santa Barbara, CA
      ** Verplex Systems Inc., Milpitas, CA
       
  • 4:30-4:45: Concluding remarks
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