Computer Architecture At UCSD

The architecture group at UCSD is at the cutting edge of innovation in processor and computer systems design. Our current projects address the current "grand challenge" of computer architecture: Finding power-efficient ways to find and exploit parallelism to continue scaling performance. We are addressing this challenge by exploring novel programming abstractions, CPU and storage system organization, execution strategies, micro-architectures, processor design methodologies, and circuit technologies. Our group consists of 3 faculty and over 20 graduate students and is well-supported through generous funding from government and industrial sources.

People | Publications | Projects | Sponsors

Dr. Steven Swanson

Dr. Michael Taylor

Dr. Dean Tullsen

Projects

Example

Arsenal: Massively Heterogeneous Multiprocessors

Growing transistor counts, limited power budgets, and the breakdown of voltage scaling currently conspire to limit the fraction of a chip that can run at full speed at one time. In this regime, reducing per-computation power requirements is one viable approach to increasing parallelism, since more computations can execute under the same power budget. The Arsenal project's goal is to synthesize a diverse set of specialized processing elements and integrate them into a single, heterogneous processor. The design of an Arsenal prototype chip is currently underway.

Faculty: Steven Swanson and Michael Taylor

The Non-volatile Systems Laboratory

The Non-volatile Systems Lab studies non-volatile, solid-state storage technologies and their applications at the architecture, system, and software levels. We develop novel system and hardware architectures for advanced non-volatile memories, characterize existing technologies, and develop techniques to ensure the security of data stored in these devices. It works with Center for Magnetic Recording Research, the San Diego Supercomputing Center, government agencies, and industrial partners to understand current and future non-volatile memory technologies and craft the system architectures, abstractions, and applications required to fully realize their potential.

Faculty: Steven Swanson

Memory Systems for Large-Scale CMP

The rise of many-core processors presents enormous challenges in the memory system. We are working to develop hardware and software techniques to increase memory system performance by intelligently and transparently managing on-chip cache capacity via software. To ground this work in reality, we have developed detailed performance models for existing and future multiprocessor systems. The models allow us both to accurately predict the performance of our techniques, but also guide the developement and refinement of future CMP memory systems.

Faculty: Dean Tullsen and Steven Swanson

PhD Students

Ikkjin Ahn
Jeffery Brown
Adrian Caulfield
Stephen Checkoway
Joel Coburn
Ayse Coskun
Arup De
Matthew Devuyst

Saturnino Garcia
Nathan Goulding
Laura Grupp
Anshuman Gupta
Donghwan Jeon
MD Kamruzzaman
Vasileios Kontorinis

Jin Seok Lee
Leo Porter
Jack Sampson
Michael Stepp
Richard Strong
Hung-Wei Tseng
Ganesh Venkatesh

MS Students

Ameen Akel
Slavik Bryksin
Jose Lugo-Martinez

Scott Ricketts
Daniel Stufflebean
Hyojin Sung

Recent Alumni

Jeremy Lau (Ph.D. 2007) → Google Labs
Erez Perelman (Ph.D. 2007) → Consulting and Guitar building
Michael Van Biesbrouck (Ph.D. 2007) → Google
Cristiano Pereira (Ph.D. 2007) → Intel
Satish Narayanasamy (Ph.D. 2007) → Assistant Professor, in EECS at University of Michigan
Rakesh Kumar (Ph.D. 2006) → University of Illinois, Urban-Champaign

[Alumni Archive]

Recent Publications

Characterizing Flash Memory: Anomalies, Observations and Applications, Laura M. Grupp, Adrian M. Caulfield, Joel Coburn, Steven Swanson, Eitan Yaakobi, Paul H. Siegel, and Jack K. Wolf, The 42nd Annual IEEE/ACM International Symposium on Microarchitecture, 2009.

McPAT: An Integrated Power, Area, and Timing Modeling Framework for Multicore and Manycore Architectures, Sheng Li, Jung Ho Ahn, Jay B. Brockman, Dean M. Tullsen, and Norman P. Jouppi, MICRO '1009 Proceedings of the 2009 42nd IEEE/ACM International Symposium on Microarchitecture, 2009.

Evaluating the impact of job scheduling and power management on processor lifetime for chip multiprocessors, Ayse K. Coskun, Richard Strong, Dean M. Tullsen, and Tajana Simunic Rosing, SIGMETRICS '09: Proceedings of the eleventh international joint conference on Measurement and modeling of computer systems, New York, NY, USA, 2009, pages 169-180.

Fast switching of threads between cores, Richard Strong, Jayaram Mudigonda, Jeffrey C. Mogul, Nathan Binkert, and Dean Tullsen, SIGOPS Operating Systems Review 43(2):35-45, 2009.

Reducing Peak Power with a Table-Driven Adaptive Processor Core, Vasileios Kontorinis, Amirali Shayan, Rakesh Kumar, and Dean Tullsen, MICRO 42: Proceedings of the 42nd annual IEEE/ACM International Symposium on Microarchitecture, New York City, NY, USA, 2009.

Creating artificial global history to improve branch prediction accuracy, Leo Porter and Dean M. Tullsen, ICS '09: Proceedings of the 23rd international conference on Supercomputing, New York, NY, USA, 2009, pages 266-275.

Mapping Out a Path from Hardware Transactional Memory to Speculative Multithreading, Leo Porter, Bumyong Choi, and Dean M. Tullsen, PACT '09: Proceedings of the 18th international conference on parallel architectures and compilation techniques, 2009.

Gordon: Using Flash Memory to Build Fast, Power-efficient Clusters for Data-intensive Applications, Adrian Caulfield, Laura Grupp, and Steven Swanson, ASPLOS 2009: Proceedings of the 14th international conference on Architectural support for programming languages and operating systems, 2009. (Selected for IEEE Micro "Top Picks" 2009).

[Publication Archive]