ISCA 2007 Main Program

Saturday, June 9th - Sunday, June 10th

Tutorials Workshops

Sunday, June 10th

7:30-9:30

Welcome Reception

Monday, June 11th

8:00-8:45	Breakfast
8:45-9:00	Welcome
9:00-10:00	SESSION 1: SPECIAL PURPOSE TO WAREHOUSE COMPUTERS Chair: Norm Jouppi, Hewlett Packard Anton, a Special-Purpose Machine for Molecular Dynamics Simulation David E. Shaw, D. E. Shaw Research, LLC Martin M. Deneroff, D. E. Shaw Research, LLC Ron O. Dror, D. E. Shaw Research, LLC Jeffrey S. Kuskin, D. E. Shaw Research, LLC Richard H. Larson, D. E. Shaw Research, LLC John K. Salmon, D. E. Shaw Research, LLC Cliff Young, D. E. Shaw Research, LLC Brannon Batson, D. E. Shaw Research, LLC Kevin J. Bowers, D. E. Shaw Research, LLC Jack C. Chao, D. E. Shaw Research, LLC Michael P. Eastwood, D. E. Shaw Research, LLC Joseph Gagliardo, D. E. Shaw Research, LLC J.P. Grossman, D. E. Shaw Research, LLC C. Richard Ho, D. E. Shaw Research, LLC Douglas J. Ierardi, D. E. Shaw Research, LLC Istvan Kolossvary, D. E. Shaw Research, LLC John L. Klepeis, D. E. Shaw Research, LLC Timothy Layman, D. E. Shaw Research, LLC Christine McLeavey, D. E. Shaw Research, LLC Mark A. Moraes, D. E. Shaw Research, LLC Rolf Mueller, D. E. Shaw Research, LLC Edward C. Priest, D. E. Shaw Research, LLC Yibing Shan, D. E. Shaw Research, LLC Jochen Spengler, D. E. Shaw Research, LLC Michael Theobald, D. E. Shaw Research, LLC Brian Towles, D. E. Shaw Research, LLC Stanley C. Wang, D. E. Shaw Research, LLC Power Provisioning for a Warehouse-sized Computer Xiaobo Fan, Google Inc. Wolf-Dietrich Weber, Google Inc. Luiz Andre Barroso, Google Inc.
10:00-10:20	Break
10:20-11:20	SESSION 2-A: TRANSACTIONS AND SYNCHRONIZATION Chair: Krste Asanovic, MIT Making the Fast Case Common and the Uncommon Case Simple in Unbounded Transactional Memory Colin Blundell, University of Pennsylvania Joe Devietti, University of Pennsylvania E Christopher Lewis, VMware, Inc. Milo M. K. Martin, University of Pennsylvania Synchronization State Buffer: Supporting Efficient Fine-Grain Synchronization on Many-Core Architectures Weirong Zhu, University of Delaware Vugranam C. Sreedhar, IBM TJ Watson Research Center Ziang Hu, University of Delaware Guang R. Gao, University of Delaware SESSION 2-B: VIRTUAL CACHES AND HIERARCHIES Chair: Margaret Martonosi, Princeton Virtual Hierarchies to Support Server Consolidation Michael R. Marty, University of Wisconsin-Madison Mark D. Hill, University of Wisconsin-Madison Virtual Private Caches Kyle J Nesbit, University of Wisconsin - Madison - ECE Department James Laudon, Sun Microsystems James E Smith, University of Wisconsin - Madison - ECE Department
11:30-12:30	FCRC Plenary Session Chuck Moore, AMD: A Framework for Innovation-Abstract
12:30-1:30	Lunch
1:30-3:30	SESSION 3-A: TRANSACTIONS Chair: Marc Tremblay, Sun An Effective Hybrid Transactional Memory System with Strong Isolation Guarantees Chi Cao Minh, Stanford University Martin Trautmann, Stanford University JaeWoong Chung, Stanford University Austen McDonald, Stanford University Nathan Bronson, Stanford University Jared Casper, Stanford University Christos Kozyrakis, Stanford University Kunle Olukotun, Stanford University Performance Pathologies in Hardware Transactional Memory Jayaram Bobba, University of Wisconsin Kevin E Moore, University of Wisconsin Haris Volos, University of Wisconsin Luke Yen, University of Wisconsin Mark D Hill, University of Wisconsin Michael M Swift, University of Wisconsin David A Wood, University of Wisconsin MetaTM/TxLinux: Transactional Memory For An Operating System Hany E. Ramadan, University of Texas at Austin Christopher J. Rossbach, University of Texas at Austin Donald E. Porter, University of Texas at Austin Owen S. Hofmann, University of Texas at Austin Aditya Bhandari, University of Texas at Austin Emmett Witchel, University of Texas at Austin An Integrated Hardware-Software Approach to Flexible Transactional Memory Arrvindh Shriraman, University of Rochester Michael F Spear, University of Rochester Hemayet Hossain, University of Rochester Virendra J Marathe, University of Rochester Sandhya Dwarkadas, University of Rochester Michael L Scott, University of Rochester SESSION 3-B: NETWORKS AND ROUTERS Chair: Michael Taylor, UCSD Rotary Router: An Efficient Architecture for CMP Interconnection Networks Pablo Abad, University of Cantabria Valentin Puente, University of Cantabria Jose Angel Gregorio, University of Cantabria Pablo Prieto, University of Cantabria Flattened Butterfly : A Cost-Efficient Topology for High-Radix Networks John Kim, Stanford University William J Dally, Stanford University Dennis Abts, Cray Inc. A Novel Dimensionally-Decomposed Router for On-Chip Communication in 3D Architectures Jongman Kim, Pennsylvania State University Chrysostomos Nicopoulos, Pennsylvania State University Dongkook Park, Pennsylvania State University Reetuparna Das, Pennsylvania State University Yuan Xie, Pennsylvania State University Vijaykrishnan Narayanan, Pennsylvania State University Mazin S. Yousif, Intel Corp. Chita R. Das, Pennsylvania State University Express Virtual Channels: Towards the Ideal Interconnection Fabric Amit Kumar, Princeton University Li-Shiuan Peh, Princeton University Partha Kundu, Intel Corp. Niraj K Jha, Princeton University
3:30-4:00	Break
4:00-5:00	SESSION 4-A: ATOMIC REGIONS AND FINE-GRAINED PARALLELISM Chair: Milo Martin, U. Penn Carbon: Architectural Support for Fine-Grained Parallelism on Chip Multiprocessors Sanjeev Kumar, Intel Corp. Christopher J Hughes, Intel Corp. Anthony Nguyen, Intel Corp. Hardware Atomicity for Reliable Software Speculation Naveen Neelakantam, University of Illinois at Urbana-Champaign Ravi Rajwar, Intel Corporation Suresh Srinivas, Intel Corporation Uma Srinivasan, Intel Corporation Craig Zilles, University of Illinois at Urbana-Champaign SESSION 4-B: CORE FUSION AND QUANTUM Chair: Doug Burger, U. Texas, Austin Core Fusion: Accommodating Software Diversity in Chip Multiprocessors Engin Ipek, Cornell University Meyrem Kirman, Cornell University Nevin Kirman, Cornell University Jose F. Martinez, Cornell University Tailoring Quantum Architectures to Implementation Style: A Quantum Computer for Mobile and Persistent Qubits Eric Chi, Princeton University Stephen A. Lyon, Princeton University Margaret Martonosi, Princeton University
6:00-10:00	Banquet at the San Diego Zoo (Sponsored by Intel)

Tuesday, June 12th

8:30-10:00	SESSION 5: STREAMS TO PHYSICS PROCESSORS Chair: Bill Dally, Stanford A 64-bit Stream Processor Architecture for Scientific Applications Xuejun Yang, National Laboratory for Paralleling and Distributed Processing, School of Computer, National University of Defense Technology Xiaobo Yan, National Laboratory for Paralleling and Distributed Processing, School of Computer, National University of Defense Technology Zuocheng Xing, National Laboratory for Paralleling and Distributed Processing, School of Computer, National University of Defense Technology Yu Deng, National Laboratory for Paralleling and Distributed Processing, School of Computer, National University of Defense Technology Jiang Jiang, National Laboratory for Paralleling and Distributed Processing, School of Computer, National University of Defense Technology Ying Zhang, National Laboratory for Paralleling and Distributed Processing, School of Computer, National University of Defense Technology Physical Simulation for Animation and Visual Effects: Parallelization and Characterization for Chip Multiprocessors Christopher J. Hughes, Intel Radek Grzeszczuk, Nokia Labs Eftychios Sifakis, Stanford University Daehyun Kim, Intel Sanjeev Kumar, Intel Andrew P. Selle, Stanford University Jatin Chhugani, Intel Matthew Holliman, Intel Yen-Kuang Chen, Intel ParallAX: An Architecture for Real-Time Physics Thomas Y. Yeh, UCLA Petros Faloutsos, UCLA Sanjay J. Patel, AGEIA Technologies Glenn Reinman, UCLA
10:00-10:20	Break
10:20-11:20	SESSION 6-A: BRICKS, MORTARS, AND MICROFLUIDICS Chair: Tim Sherwood, UC Santa Barbara Architectural Implications of Brick and Mortar Silicon Manufacturing Martha Mercaldi Kim, University of Washington Mojtaba Mehrara, University of Michigan Mark Oskin, University of Washington Todd Austin, University of Michigan AquaCore: A Programmable Architecture for Microfluidics Ahmed M Amin, School of Electrical & Computer Engineering, Purdue University Mithuna Thottethodi, School of Electrical & Computer Engineering, Purdue University T N Vijaykumar, School of Electrical & Computer Engineering, Purdue University Steven Wereley, School of Mechanical Engineering, Purdue University Stephen C Jacobson, Department of Chemistry, Indiana University SESSION 6-B: MEMORY CONSISTENCY Chair: Mark Hill, Wisconsin Mechanisms for Store-wait-free Multiprocessors Thomas F Wenisch, Carnegie Mellon University Anastasia Ailamaki, Carnegie Mellon University Babak Falsafi, Carnegie Mellon University Andreas Moshovos, University of Toronto BulkSC: Bulk Enforcement of Sequential Consistency Luis Ceze, University of Illinois James Tuck, University of Illinois Pablo Montesinos, University of Illinois Josep Torrellas, University of Illinois
11:30-12:30	FCRC Plenary Session David Culler, UC Berkeley and Deborah Estrin, UCLA: Wireless Sensing - the Internet's Front-Tier
12:30-2:00	Awards Lunch
2:00-3:30	SESSION 7-A: POWER AND THERMAL Chair: Partha Ranganathan, Hewlett Packard Limiting the Power Consumption of Main Memory Bruno Diniz, Federal University of Minas Gerais Dorgival Guedes, Federal University of Minas Gerais Wagner Meira Jr., Federal University of Minas Gerais Ricardo Bianchini, Rutgers University Power Model Validation Through Thermal Measurements Francisco Javier Mesa-Mar tinez, UC Santa Cruz Joseph Nayfach-Battilana, UC Santa Cruz Jose Renau, UC Santa Cruz Thermal Modeling and Management of DRAM Memory Systems Jiang Lin, Iowa State University Hongzhong Zheng, University of Illinois at Chicago Zhichun Zhu, University of Illinois at Chicago Howard David, Intel Corp. Zhao Zhang, Iowa State University SESSION 7-B: CLOCKS, SCHEDULING, AND STORES Chair: Todd Austin, U. Michigan ReCycle: Pipeline Adaptation to Tolerate Process Variation Abhishek Tiwari, University of Illinois at Urbana-Champaign Smruti R. Sarangi, University of Illinois at Urbana-Champaign Josep Torrellas, University of Illinois at Urbana-Champaign Matrix Scheduler Reloaded Peter G. Sassone, Intel Microarchitecture Research Lab (MRL) Jeff Rupley II, Intel Microarchitecture Research Lab (MRL) Edward Brekelbaum, Intel Microarchitecture Research Lab (MRL) Gabriel H. Loh, Georgia Inst of Technology Bryan Black, Intel Microarchitecture Research Lab (MRL) Late-Binding: Enabling Unordered Load-Store Queues Simha Sethumadhavan, Department of Computer Sciences, The University of Texas at Austin Franziska Roesner, Department of Computer Sciences, The University of Texas at Austin Joel S Emer, VSSAD, Intel Corporation Doug Burger, Department of Computer Sciences, The University of Texas at Austin Stephen W. Keckler, Department of Computer Sciences, The University of Texas at Austin
3:30-4:00	Break
4:00-5:30	SESSION 8-A: MEMORY AND CACHES Chair: Luiz Barroso, Google Comparing Memory Systems for Chip Multiprocessors Jacob Leverich, Stanford University Hideho Arakida, Stanford University Alex Solomatnikov, Stanford University Amin Firoozshahian, Stanford University Mark Horowitz, Stanford University Christos Kozyrakis, Stanford University Interconnect Design Considerations for Large NUCA Caches Naveen Muralimanohar, Unversity of Utah Rajeev Balasubramonian, University of Utah Adaptive Insertion Policies for High Performance Caching Moinuddin K Qureshi, The University of Texas at Austin Aamer Jaleel, Intel Yale N. Patt, The University of Texas at Austin Simon C. Steely, Intel Joel Emer, Intel SESSION 8-B: EXPERIENCE AND METHODOLOGY Chair: Joel Emer, Intel Performance and Security Lessons Learned from Virtualizing the Alpha Processor Paul A. Karger, IBM Thomas J. Watson Research Center Automated Design of Application Specific Superscalar Processors: An Analytical Approach Tejas S Karkhanis, University of Wisconsin - Madison James E Smith, University of Wisconsin - Madison Analysis of Redundancy and Application Balance in the SPEC CPU2006 Benchmark Suite Aashish Phansalkar, ECE Department, The University of Texas at Austin Ajay Joshi, ECE Department, The University of Texas at Austin Lizy K John, ECE Department, The University of Texas at Austin
7:00-8:30	Sigarch/TCCA Business Meeting

Wednesday, June 13th

8:30-10:00 Parallel Session	SESSION 9-A: CONTROL INDEPENDENCE AND PREDICTION Chair: Craig Zilles, UIUC VPC Prediction: Reducing the Cost of Indirect Branches via Hardware-Based Dynamic Devirtualization Hyesoon Kim, UT-Austin Jose A. Joao, UT-Austin Onur Mutlu, Microsoft Research Chang Joo Lee, UT-austin Yale N. Patt, UT-Austin Robert Cohn, intel Ginger: Control Independence Using Tag Rewriting Andrew D Hilton, University of Pennsylvania Amir Roth, University of Pennsylvania Transparent Control Independence (TCI) Ahmed S. Al-Zawawi, Department of Electrical and Computer Engineering, North Carolina State University Vimal K. Reddy, Department of Electrical and Computer Engineering, North Carolina State University Eric Rotenberg, Department of Electrical and Computer Engineering, North Carolina State University Haitham H. Akkary, Digital Enterprise Group, Intel Corporation
9:00-10:00 Parallel Session	SESSION 9-B: FAULTS Chair: Josep Torrellas, UIUC Examining ACE Analysis Reliability Estimates Using Fault-Injection Nicholas J Wang, University of Illinois Aqeel Mahesri, University of Illinois Sanjay J Patel, University of Illinois Configurable Isolation: Building High Availability Systems with Commodity Multi-Core Processors Nidhi Aggarwal, Computer Sciences Department, University of Wisconsin-Madison Parthasarathy Ranganathan, Hewlett Packard Labs Norman P Jouppi, Hewlett Packard Labs James E Smith, Electrical and Computer Engineering, University of Wisconsin-Madison
10:00-10:20	Break
10:20-11:20	SESSION 10-A: SECURITY Chair: Glenn Reinman, UCLA Raksha: A Flexible Information Flow Architecture for Software Security Michael Dalton, Stanford University Hari Kannan, Stanford University Christos Kozyrakis, Stanford University New Cache Designs for Thwarting Software Cache-based Side Channel Attacks Zhenghong Wang, Princeton University Ruby B Lee, Princeton University SESSION 10-B: VULNERABILITIES Chair: Sarita Adve, UIUC Mechanisms for Bounding Vulnerabilities of Processor Structures Niranjan Kumar Soundararajan, The Pennsylvania State University Angshuman Parashar, The Pennsylvania State University Anand Sivasubramaniam, The Pennsylvania State University Dynamic Prediction of Architectural Vulnerability from Microarchitectural State Kristen R. Walcott, University of Virginia Greg Humphreys, University of Virginia Sudhanva Gurumurthi, University of Virginia
11:30-12:30	FCRC Plenary Session Avi Wigderson, Princeton: The Art of Reduction