**Online Required Textbook: Digital Design by F. Vahid**

Students are required to have an account in zyBooks and to complete assigned exercises at a due time.

It is important that you use the SAME username for both TED and ZyBooks. Here are the instruction on how to change the subscription details Any of the students can update their own subscription details from within the ZyBook, simply click on the action menu in the top right corner and select 'Show subscription'. From there you may update your subscription information.

**Recommended Textbooks: (reserved at Library)**

**R1: Digital Design and Computer Architecture**by David Mooney Harris and Sarah L. Harris**R2: Digital Design with RTL Design, VHDL, and Verilog**by Frank Vahid**R3: (Part III of) Digital Systems and Hardware/Firmware Algorithms**by M.D. Ercegovac and T. Lang

- 10% zyBook weekly activities
- 5% Homeworks
- 5% In class participation using clickers.
- 25% Midterm One (1/25/16)
- 25% Midterm Two (2/17/16)

- 30% Final (3-6PM, 3/14/16 at Recreational Gym)

- Assignments should be submitted via TED.
- All zyBook activities will be graded based on CORRECTNESS. Multiple attempts will not be marked down as long as you get the right answer.
- All written homeworks must be done individually.
- No extensions will be given on assignments except for real medical emergency.
- If more than 70% of the class fill out CAPE evaluations, lowest homework score will be dropped.

Week | Lecture | Homework | Required zyBook Weekly Activities | Recommended Readings |
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1 | Course Overview - The digital abstraction and basic logic gates [Lecture 1] |
[Homework 1] Due 1159PM, Tu 1/12/16 [Solution] | Finish zyBook activities in sections 1.8, 1.10, and 1.11 before Sun (01/10)@10pm | zyBook 1.6-13, 2.4 |

Combinational Logic Specification and Realization: Truth tables, Boolean Algebra, Boolean Equations, Boolean Algebra Axioms - DeMorgan's, Consensus, Specifying Combinational Circuits: POS and SOP canonical forms, [Lecture 2] [Lecture 2+hand notes]@1/22/16. |
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2 | Combinational Circuits: Logic minimization with 2-, multivariable- K-maps [Lecture 3], and [Lecture 3+hand notes]@1/15/16. | [Homework 2] Due 1159PM, Th 1/21/16 [Solution] | Finish zyBook activities in sections 1.16, 2.1, 2.2, and 2.3 before Sun (01/17)@10pm | zyBook 1.14-16, 2.1-3 |

K-Maps (essential and non-essential prime implicants and implicates) K-map to product of sum minimization K-Maps in higher dimensions [Lecture 4], and [Lecture 4+hand notes]@1/22/16. | Finish zyBook activities in sections 2.5-6, and 4.1-3 before Sun (01/24)@10pm | zyBook 2.5-8, 4.1-3 | ||

3 | K-Maps (essential and non-essential prime implicates) K-map to product of sum minimization K-Maps in higher dimensions [Lecture 5], and [Lecture 5+hand notes]@1/22/16. | |||

Previous midterm 1 problems, solutions and rubrics. [Midterm 1 Problems, Fall 2012]. [Midterm 1 Solutions, Fall 2012]. [Midterm 1, Spring 2014]. [Midterm 1 Problems, Fall 2014]. [Midterm 1 Solutions, Fall 2014]. | ||||

4 | Midterm1, solution and rubric. [Midterm1 Solution, Winter 2016]. | |||

Universal set and XOR, NAND, NOR gates, block diagram transfers [Lecture 6], and [Lecture 6+hand notes]@2/12/16. | Finish zyBook activities in sections 3.1-2 before Sun (01/31)@10pm | zyBook 3.1-3 | ||

5 | Sequential Networks: Introduction and memory components [Lecture 7], and [Lecture 7+hand notes]@2/1/16. | [Homework 3] Due 1159PM, Th 2/4/16 [Solution] | Finish zyBook activities in sections 3.4-8, 3.11-12 before Sun (02/7)@10pm | zyBook chapter 3 |

Sequential Networks: Specification and analysis [Lecture 8], and [Lecture 8<+hand notes/a>]@2/12/16. | [Homework 4] Due 1159PM, Th 2/11/16 [Solution] | |||

6 | Sequential Networks: Implementation [Lecture 9], and [Lecture 9+hand notes]@2/10/16. | Finish zyBook activities in sections 3.13 before Sun (02/14)@10pm | zyBook chapter 3 | |

Previous midterm 1 problems, solutions and rubrics. [Midterm 2 Problems, Fall 2012]. [Midterm 2 Solutions, Fall 2012]. [Midterm 2 Questions + Solutions, Spring 2014]. [Midterm 2 Questions + Solutions, Fall 2014]. | ||||

7 | Midterm2, solution and rubric. [Midterm2 Solution, Winter 2016]. | |||

Sequential Networks: Timing [lecture 10 ], and [lecture 10+hand note ]@2/24/16. | Finish zyBook activities in sections 2.7-8, 4.5-6 (Multiplexers, Decoders and Registers) before Sun (02/21)@10pm | zyBook chapters 2, 4 | ||

8 | Standard Combinational Modules: Decoder and Encoder [lecture 11 ], and [lecture 11+hand note ]@2/24/16; Mutiplexer and Demultiplexer [lecture 12 ], and [lecture 12+hand note ]@2/29/16; Adders, Comparators [lecture 13 ] (skip for now). | [Homework 5] Due 1159PM, Th 3/3/16 [Solution] | Finish zyBook activities in sections 4.1-4 (Adders, Subtractors and Comparators) before Sun (02/28)@10pm | zyBook chapter 4 |

9 | System Designs: Introduction, [lecture 14 ], and [lecture 14+hand note ]@2/29/16 (the hand note of 3/2/16 is corrupted and not available); Implementation, [lecture 15 ], and [lecture 15+hand note ]@3/7/16. | Finish zyBook activities in section 3.10 (State encodings), and sections 7.1-5 (Vereilog HDL) before Sun (03/6)@10pm | zyBook chapters 3 and 7; and R3 chapter 9:Hardware/Firmware Implementation posted on TED | |

10 | Exercise and previous exam: [exercise], [solution]; [midterm 3 and solution of Fall 2014]. | No hw due this week | No exercise due this week | R3 chapter 9:Hardware/Firmware Implementation posted on TED |

Useful Videos (Courtesy of Dao Lam, previous TA for CSE140) [video on Data subsystem] [video on Control subsystem] [video on One-hot state machine] |
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11 | Final (Midterm3), solution and rubric. [Midterm3 Solution, Winter 2016]. |