|CSE 240A: |
Graduate Computer Architecture
Announcements - Assignments - Project
Last updated: Monday, 01-Apr-2013 20:51:14 PDT
Join and monitor this google group immediately:
|Project||30%||To be discussed.|
|Mini Quiz||9.9999%||Tests prerequisities incl. pipelining, caches, VM.|
|Final||30%||Cumulative; closed book.|
|Homework||7%||Homeworks assigned through the course.
They aren't worth much, but if you don't do them, you will probably bomb the exams.|
Check-/Check+/Check Due in TA's mailbox 5 minutes before class.
|Paper Summaries||7%||Periodically through the class; submit via google form at least 1 hour before class.|
|Class Participation||6% or more||In class, or in the google group|
|Tue, January 08||Overview, Administrivia, Tech Trends||Read Appendix C (if your arch is rusty), 1.1-1.12||slides|
|Thu, January 10||Technology||Read Appendix A (if your arch is rusty); Read this paper for Tues, Jan 15.||slides|
|Tue, January 15||Technology Scaling, Performance||slides|
|Thu, January 17|
|Tue, January 22||Performance||Read Ultrasparc I and III papers.||slides|
|Thu, January 24||Single Issue, Exceptions, Pipeline Evolution||Read 3.1, 3.2, 3.3, 3.9:"Increasing Fetch Bandwidth"|
|Tue, January 29||UltraSparc, continued; Front Ends. QUIZ||Read 3.4-3.8,3.12-3.13: Out-of-order Superscalars||slides|
|Thu, January 31||Front Ends||Read MIPS R10K and 21264 papers.|
|Tue, February 05||In-order Superscalar||slides|
|Thu, February 07||Out-of-order||Review B.1-B.3; Read 2.1-2.3;||slides|
|Tue, February 12||Out-of-order||Review B.4-B.5; Read 2.4-2.9;||slides|
|Thu, February 14||ROB|
|Tue, February 19||MIPS/21264|
|Thu, February 21||MIDTERM EXAM review (subj to change)|
|Tue, February 26||MIDTERM EXAM (subj to change)|
|Thu, February 28||Caches|| Read Exploiting choice: instruction fetch and issue on an implementable simultaneous multithreading processor, Dean M. Tullsen, Susan J. Eggers, Joel S. Emer, Henry M. Levy, Jack L. Lo, and Rebecca L. Stamm, ISCA '96: Proceedings of the 23rd annual international symposium on Computer architecture, New York, NY, USA, 1996, pages 191-202.|
Also read Niagara: A 32-way Multithreaded Sparc Processors, IEEE Micro 25(2):21-29, 2005.
|Tue, March 05||Caches; Virtual Memory|
|Thu, March 07||Multithreading|| Project 1 Due; |
Read The Raw Microprocessor: A Computational Fabric for Software Circuits and General Purpose Programs,IEEE Micro, March/April 2002. (pdf)
Read Tilera ISSCC 2008 Paper
|Tue, March 12||Tiled Cores|| Project 1 Award Ceremony (approx) |
Read Single-ISA Heterogeneous Multi-Core Architectures: The Potential for Processor Power Reduction and
Read Conservation Cores: Reducing the Energy of Mature Computations
|Thu, March 14||Multicore||Prepare for Final||slides|
3/19/13 - Prefetcher Project Results are up!
2/21/13 - Midterm Review slides have been posted.
1/8/13 - If you would like to contact Michael or Manoj by e-mail, please include the phrase "CSE240A" in the subject so that your e-mail is not eaten by spam filters.
1/8/13 - The course website is now up and functional. Please check here regularly for announcements.
1/8/13 - Paper Analysis Submission site is up.
Note: If not otherwise specified, the readings and writeups are assigned on the day that they are listed
and due at the next class. (Yes, you do a individual writeup for each paper.)
* For all homeworks, please create a cover page. The cover page should contain the following info: course (CSE240A), term (Winter 2013), homework number (e.g. HW #1), name(s), and date. To aid in fair grading, please do not put your name(s) on any page other than the cover page.
* You are STRONGLY RECOMMENDED to work in groups of 2. If working with a group, you only need to submit one writeup. All members will receive the same grade. Typed solutions will make the TA smile but are not strictly required.
* All homeworks should be submitted to the TA in their mailbox (room 2237 in the CSE building) on or before the deadline. No late assignments will be accepted! DO NOT submit your homework via e-mail.