Please Note:  All homework assignments must be typed, unless otherwise specified.

Please make sure you understand the class integrity poliy before you begin doing any of the homeworks!

Homework Assignments:

• hw #1 -- due Wednesday, January 14
  • P&H 2.2, 2.4, 2.6, 2.9 (note 1), 2.27 (note 2), 2.30, 2.31, 2.37 (only do rows 1, 2, 3, 6, 8, 11)
  • note 1 -- you can not assume the register $s0 has an initial value (such as zero). Also, solve this problem the way an unoptimized compiler would -- implement the effect of each instruction individually (regardless of what instructions may surround it).
  • note 2 -- the answer to this problem is D. Here's what I really want you to do with this problem. First, find the two errors in the code. Second, explain why the answer is D and not B.
• hw #2 -- due Wednesday, January 28
  • P&H 4.2, 4.7, 4.9, 4.10, 4.12, 4.17, 4.19, P1, 3.2, 3.5, 3.10, 3.31
  • P1: Machine B runs at 2 GHz and has a CPI of 1.3 for a particular program. Machine C, which runs at 5 GHz, has a CPI of 2.4 for that program, while executing 20% more instructions. Which machine is faster? What is the speedup over the slower machine?
• hw #3 -- due Wednesday, Feb 4.
  • P&H 5.2, 5.8, 5.19, 5.27*, 5.30**, 5.34***, P2.
  • *in the older version of the book, this is problem 5.29, but in either case, should have parts a-f.
  • **in the older version of the book, this is problem 5.32, and involves the instruction "lui".
  • ***in the older version of the book, this is problem 5.36 and starts "Two important parameters". However there is a typo. So use the following clock frequencies M1: 4GHz, M2: 3.2GHz, M3:2.8 GHz.
  • ***(part 2) For either version, just use the following instruction frequencies (loads 28%, stores 10%, reg-reg ALU 43%, branch 16%, jump 3%).
  • P2 -- Give an example of one Intel IA32 instruction that could not be implemented on a single-cycle processor, assuming reg file and memory elements similar to what we used in class.
  • these might be useful: fig 5.17, fig 5.28.
• hw #4 -- due Wednesday, Feb 25
  • P&H (5.26, 5.33, 5.35**)*, 6.1, 6.2b,c, 6.4, 6.6, 6.13***, 6.14****, P3, P4, W1.
    • *in the older printing, these are problems 5.28, 5.35, and 5.37, and begin "The concept", "Consider a change", and "Your friends", respectively
    • **use the instruction frequencies above from the last hw set, rather than the SPEC frequencies mentioned in the problem.
    • ***use this figure instead.
    • ****use figure 6.32, not 6.30, but also refer to 6.27 for the control signals
    • P4 -- using figure 6.41 as a template, highlight all data paths active (active means carrying data that will actually be used to complete the instruction) for the following code, in the cycle that the lw is in the wb stage:
      • lw $5, 1000($4)
      • add $1, $3, $5
      • sw $10, 1004($4)
      • sub $3, $10, $1
    • P5 -- Show forwarding and stalls for the following code, assuming the pipelined machine from figure 6.36. Show it the way we did in class, with IF ID EX M WB, and arrows and bubbles.

      lw R3, 100(R5)
      add R6, R3, R2
      sub R9, R3, R8
      lw R1, 2000(R9)
      add R5, R4, R3
      addi R7, R1, #8

    • W1 -- Using the web, find the number of pipeline stages for the following processors: Intel Pentium 4, Intel Core 2 Duo, AMD Opteron, Intel Itanium 2.
• hw #5 -- due Wednesday, March 4.
  • P&H 6.18, 6.19, 6.35, 6.36, P6, P7. 7.3, 7.9*, 7.10*
    • P6 -- Circle all of the instructions in the following code that could safely be moved into the branch delay slot (replacing the nop). Assume other instructions cannot be otherwise reordered or changed. Assume you know nothing about the missing code (the ...).

      add R1, R2, R3
      sub R5, R2, R3
      and R7, R5, R2
      lw R8, 1000(R5)
      beq R7, r15, label:
      nop
      add R6, R7, R5
      sub R5, R7, R5
      lw R9, 2000(R2)
      ...
      label: add R9, R7, R5
      addi R5, R0, #0
      ...

    • P7 -- Assume the same code as P5, but running on a different pipeline. In this case, the machine has the following stages: IF ID X1 X2 M1 M2 WB. That is, ALU computation takes two cycles/stages, as does data memory access (the data needed for the alu or memory must be available at the beginning of X1 or M1, and the results are not available until the end of X2 or M2, respectively). Show forwarding and stalls for the code.
    • *To be consistent with our discussions in class, multiply all addresses in the problem by 4 to get the byte addresses. Thus, addresses are 8, 12, 44, ... (this will not change the answers).
• hw #6 -- due Wednesday, March 11.
  • P&H 7.12, 7.18, 7.25*, 7.32, 7.35, 7.39, P8, P9, P10, P11, W2
    • *see note above for 7.9
    • P8 -- Program P running on Processor C achieves an instruction cache miss rate of 6% and a data cache miss rate of 9%. Assume a miss penalty of 25 cycles, that 20% of all instructions are loads, and that we never stall for stores. If the base CPI (ignoring the effect of cache misses) is 1.3, what is the total CPI?
    • P9 -- The equation for MCPI in class assumed a single level memory hierarchy. Derive the MCPI equation for a 2-level cache configuration with separate data and instruction L1 caches, backed up by a unified L2 cache. Use the terms L1DMR, L1IMR, L2MR, L1MP, L2MP, etc.
    • P10 -- For an S KB, n-way set-associative cache with block size of B bytes, what is the size of a tag if memory addresses are 64 bits.
    • P11 -- Given what you now know about simple pipelined processors, as well as modern processors, give me an idea for performance improvement for future processors. Be creative!
    • W2 -- Using the web, find the on-chip cache configuration (as much detail as you can find) for the following processors: Intel Core i7, Intel Core 2 Quad, AMD Phenom X4.

Note, the homework may include some problems on the CD and not in the book, and even include some problems ("For More Practice" from the CD) for which they make the solutions readily available. For those ("for more practice") problems only, you may consult the answers, but please do so only after solving them (then you can go back and correct).

Very approximate Reading and Exam Schedule:
 

Date	Topic	Critical	Important	Informative
Jan 5	Introduction	1.2	-	1.1, 1.3, 1.4
Jan 7	ISA	2.1-2.6,2.9	2.13,2.15,2.16	2.7,2.8,2.10-2.12
Jan 12	ISA	-	-	-
Jan 14	Performance	4.1-4.3,4.5	4.4	-
Jan 19	Computer Arithmetic	3.1-3.4,B.5		B.6
Jan 21		3.5-3.6	3.8	3.7
Jan 26	Single-Cycle CPU	5.1,5.3,5.4	5.2
Jan 28	Single-Cycle CPU Control, Multi-cycle CPU	5.5		C.3
Feb 2	Microprogramming and Exceptions	5.6		5.7
Feb 4		6.1,6.2
Feb 9	Pipelining	6.4,6.5
Feb 11	Midterm
Feb 16	Holiday
Feb 18	Data Hazards	6.6		6.8
Feb 23	Control Hazards	6.9, 6.10
Feb 25	Advanced Pipelining	7.1-7.2
Feb 22	Cache Basics
Mar 2
Mar 4	Better Caches	7.3, 7.5	7.6
Mar 9
Mar 11	Multiprocessing and Multithreading
Mar 16	Final, 3:00