CSE140L Schedule

Date	Topic	Required Reading	Assignments
W 1/7	Introduction	Ch. 1, 9.4, B.1, B.4-7	Lab 1 out
W 1/14	Timing, Mux, Demux, Adders	Ch. 3.5, 4.2, 5.6
W 1/21	Verilog	Ch. 3.6, Verilog handout	Lab 1 due Lab 2 out
W 1/28	Verilog and FFs	Ch. 6, App. C
W 2/4	FFs and FSMs	Ch. 6, Ch. 7	Lab 2 due Lab 3 out
W 2/11	FSMs and Verilog	Ch. 7, 8
W 2/18	Memory, PLDs	Ch. 9, 10	Lab 3 due Lab 4 out
W 2/25	PLDs cont.; RTL	Ch. 10; RTL handout
W 3/4	CPU design	Ch. 1-10
W 3/11	RTL synthesis and review	Ch. 1-10, RTL handout	Lab 4 due
M 3/16	Final exam 3-6pm		Previous final Previous final solution