CSE140 Schedule

Date	Topic	Required Readings	Assignments
T 1/6	Introduction Number Systems	Ch. 1, Appendix A Ch. 2.1	HW 1 out (assignment)
Th 1/8	Boolean Algebra Logic Gates	Appendix B.1, B.4-7, Ch. 2
T 1/13	Two-Level Logic K-maps Logic Simplification	Ch. 2	HW 1 due (solutions) HW 2 out (assignment)
Th 1/15	Logic Simplification Algorithms Mux/Demux Adders	Ch 3.1, 3.2, 3.3
T 1/20	Two and multi-level logic Regular logic implementation	Ch. 3.5, Ch 4.1-3	HW 2 due (solutions) HW 3 out (assignment)
Th 1/22	Arithmetic circuits ALU	Ch. 5.5-7
T 1/27	Design examples Sequential Logic Design	Ch. 5, 6	HW 3 due (solutions) HW 4 out (assignment)
Th 1/29	MIDTERM #1: Same time and location as lecture		Old midterm #1 Old midterm #1 sol Midterm #1 solution
T 2/3	No class		HW 4 due (solutions) HW 5 out (assignment)
Th 2/5	Finite State Machines	Appendix C, Ch. 7
T 2/10	State minimization and assignment	Ch. 8	HW 5 due (solutions) HW 6 out (assignment)
Th 2/12	State assignment and partitioning	Ch. 8
T 2/17	FSM implementations and examples	Ch. 9, 10.1-3	HW 6 due (solutions) HW 7 out (assignment)
Th 2/19	MIDTERM #2: Same time and location as lecture		Old midterm #2 sol Midterm #2 solution
T 2/24	Memory	Ch. 10.4-6	HW 7 due (solutions) HW 8 out (assignment)
Th 2/26	RTL design	RTL Handout
T 3/3	RTL design cont.	RTL Handout	HW 8 due (solutions) HW 9 out (assignment)
Th 3/5	Discussion session
T 3/10	Simple processor design	CPU Handout	HW 9 due (solutions)
Th 3/12	Final exam review		Old final exam Old final exam sol
Th 3/19	Final exam: 3-6pm