Due         | Item
|
---|
Tu 1-8 | First Class.
|
Th 1-10 | Multiprocessors / Coherence H&P 3rd ed. 6.1 - 6.6 (esp 6.3 and 6.5); H&P 4th ed.: 4.1-4.5
|
Tu 1-15 | Tiled Microprocessors
Tiled Microprocessors are interesting because they blur the boundaries between multiprocessors and microprocessors.
|
The Raw Microprocessor: A Computational Fabric for Software Circuits and General Purpose Programs,
by Michael Bedford Taylor, Jason Kim, Jason Miller, David Wentzlaff, Fae Ghodrat, Ben Greenwald, Henry Hoffman, Jae-Wook Lee, Paul Johnson, Walter Lee, Albert Ma, Arvind Saraf, Mark Seneski, Nathan Shnidman, Volker Strumpen, Matt Frank, Saman Amarasinghe and Anant Agarwal.
IEEE Micro, March/April 2002.
|
Evaluation of the Raw Microprocessor: An Exposed-Wire-Delay Architecture for ILP and Streams,
by Michael Bedford Taylor, Walter Lee, Jason Miller, David Wentzlaff, Ian Bratt, Ben Greenwald, Henry Hoffmann, Paul Johnson, Jason Kim, James Psota, Arvind Saraf, Nathan Shnidman, Volker Strumpen, Matt Frank, Saman Amarasinghe, and Anant Agarwal.
Proceedings of the International Symposium on Computer Architecture, June 2004.
|
Space-Time Scheduling of Instruction-Level Parallelism on a Raw Machine,
by Walter Lee, Rajeev Barua, Matthew Frank, Devabhaktuni Srikrishna, Jonathan Babb, Vivek Sarkar, and Saman Amarasinghe.
Proceedings of the Eighth International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS-VIII), San Jose, CA, October 4-7, 1998.
|
Th 1-17
| Coherence
|
|
M. M. K. Martin,
M. D. Hill, and D. A. Wood, ``Token coherence: decoupling
performance and correctness,'' in ISCA '03: Proceedings of the
30th annual international symposium on Computer architecture,
pp. 182-193, 2003 link.
|
|
D. Lenoski, J. Laudon,
K. Gharachorloo, A. Gupta, and J. Hennessy, ``The
directory-based cache coherence protocol for the DASH multiprocessor,''
in ISCA '90: Proceedings of the 17th annual international
symposium on Computer Architecture, pp. 148-159, 1990 link.
|
|
OPTIONAL (DASH performance)
D. Lenoski, J. Laudon, T. Joe, D. Nakahira,
L. Stevens, A. Gupta, and J. Hennessy, ``The DASH
prototype: implementation and performance,'' in ISCA '98: 25
years of the international symposia on Computer architecture (selected
papers), pp. 418-429, 1998 link.
|
Tu 1-23
| Tiled 2
|
|
K. Sankaralingam,
R. Nagarajan, H. Liu, C. Kim, J. Huh,
D. Burger, S. W. Keckler, and C. R. Moore, ``Exploiting
ILP, TLP, and DLP with the polymorphous TRIPS architecture,'' SIGARCH
Comput. Archit. News, vol. 31, no. 2, pp. 422-433,
2003 link.
|
|
S. Swanson,
A. Schwerin, M. Mercaldi, A. Petersen, A. Putnam,
K. Michelson, M. Oskin, and S. J. Eggers, ``The
WaveScalar Architecture.''
To Appear in ACM Transactions On Computer Systems. link
|
Th 1-25
| Consistency
|
|
S. V. Adve and
K. Gharachorloo, ``Shared Memory Consistency Models: A Tutorial,''
tech. rep., DEC WRL, 1995 link.
|
Tu 1-30
| Consistency 2
|
| V. S. Pai,
P. Ranganathan, S. V. Adve, and T. Harton, ``An
evaluation of memory consistency models for shared-memory systems with
ILP processors,'' in ASPLOS-VII: Proceedings of the seventh
international conference on Architectural support for programming
languages and operating systems, pp. 12-23, 1996 link. |
| C. Gniady, B. Falsafi,
and T. N. Vijaykumar, ``Is SC + ILP = RC?,'' in ISCA '99:
Proceedings of the 26th annual international symposium on Computer
architecture, pp. 162-171, 1999 link. |
| OPTIONAL (but mind-bending)
J. Manson, W. Pugh,
and S. V. Adve, ``The Java memory model,'' in POPL '05:
Proceedings of the 32nd ACM SIGPLAN-SIGACT Symposium on Principles of
programming languages, pp. 378-391, 2005 link. |
Th 2-1
| Synchronization
|
|
H&P 4th ed.: 4.5
|
|
M. Herlihy, ``A methodology
for implementing highly concurrent data structures,'' in PPOPP
'90: Proceedings of the second ACM SIGPLAN symposium on Principles
& practice of parallel programming, pp. 197-206, 1990 link. |
Tu 2-6
| Transactions I
|
| L. Hammond, V. Wong,
M. Chen, B. D. Carlstrom, J. D. Davis,
B. Hertzberg, M. K. Prabhu, H. Wijaya,
C. Kozyrakis, and K. Olukotun, ``Transactional Memory
Coherence and Consistency,'' in ISCA '04: Proceedings of the 31st
annual international symposium on Computer architecture,
p. 102, 2004 link. |
| M. Herlihy and
J. E. B. Moss, ``Transactional memory: architectural support
for lock-free data structures,'' in ISCA '93: Proceedings of the
20th annual international symposium on Computer architecture,
pp. 289-300, 1993 link. |
Th 2-14
| Transactions II
|
| R. Rajwar, M. Herlihy,
and K. Lai, ``Virtualizing Transactional Memory,'' in ISCA
'05: Proceedings of the 32nd Annual International Symposium on Computer
Architecture, pp. 494-505, 2005 link. |
| B. Saha and A.-R.
A.-T. Q. Jacobson, ``Architectural Support for Software
Transactional Memory,'' in MICRO '06: Proceedings of the 39th
international symposium on Microarchitecture, 2006.
|
Tu 2-19
| Streaming
|
|
J. H. Ahn, W. J.
Dally, B. Khailany, U. J. Kapasi, and A. Das,
``Evaluating the Imagine Stream Architecture,'' in ISCA '04:
Proceedings of the 31st annual international symposium on Computer
architecture, p. 14, 2004 link.
|
|
Michael Gordon, William Thies, Michal Karczmarek, Jasper Lin, Ali S. Meli, Christopher Leger, Andrew A. Lamb, Jeremy Wong, Henry Hoffman, David Z. Maze, and Saman Amarasinghe. A Stream Compiler for Communication-Exposed Architectures. In ASPLOS 2002, San Jose, CA USA, October, 2002. (Paper: PDF)
|
Tu 2-26
| M. Baron, ``The Cell, At
One,'' Microprocessor Report, March 2006 link. |
| Overview of the Architecture, Circuit Design, and Physical Implementation of a First-Generation Cell Processor, by Pham et al.
IEEE Journal of Solid-State Circuits, January 2006.
|
| The Microarchitecture of the Synergistic Processor for a Cell Processor, by Flachs et al.
IEEE Journal of Solid-State Circuits, January 2006.
|
Th 2-28 | CMP
|
| R. Kumar, D. M.
Tullsen, P. Ranganathan, N. P. Jouppi, and K. I. Farkas,
``Single-ISA Heterogeneous Multi-Core Architectures for Multithreaded
Workload Performance,'' in ISCA '04: Proceedings of the 31st
annual international symposium on Computer architecture,
p. 64, 2004 link. |
| J. Huh, D. Burger, and
S. W. Keckler, ``Exploring the Design Space of Future CMPs,'' in PACT
'01: Proceedings of the 2001 International Conference on Parallel
Architectures and Compilation Techniques, pp. 199-210, 2001 link. |
Tu 3-4 | Interconnects
|
| H&P3 8.1-8.5, 8.9 or
H&P4 E.1-E.6, E.10
|
|
|
Th 3-6 | Interconnects II
|
| R. Kumar, V. Zyuban,
and D. M. Tullsen, ``Interconnections in Multi-Core Architectures:
Understanding Mechanisms, Overheads and Scaling,'' in ISCA '05:
Proceedings of the 32nd Annual International Symposium on Computer
Architecture, pp. 408-419, 2005 link. |
|
|
Tu 3-11 | No class
|
|
Th 3-13 | Project Presentations
|
|