cse141L Lab 3: Fetch Unit - Control


January 19

Reminder: Lab 2 is to be completed in groups of two. Select your partner wisely. I'm very hesitant to allow changes to group membership once they have formed. You and your partner should submit a single write up, etc. etc.

Due: February 1


In Lab 3, you will complete the fetch unit you worked on in Lab 2. Although you have implemented a datapath for the fetch unit, the design is incomplete without control logic. In this lab you will also validate your implementation against given test benches, and find its achievable cycle time.

Support the New FIFO Wrapper

How to use the new FIFO wrapper

In lab 3, a new FIFO wrapper is provided to more clearly convey the FIFO semantics covered in the lecture, and to provide portability between different types of FPGAs. To use the new FIFO module, follow the instructions below.

Semantics of the FIFO Wrappers

Fetch Unit Control Implementation

Complete your design using the datapath you implemented in lab 2. For a description of each signal, refer to the following subsections. You will be validating your implementation along the way you answer questions below. Keep your verilog as clean as possible. Naming convention, proper indentation, and style will be graded (10p). Make sure your verilog file is readable in the Xilinx ISE editor.

Feel free to change internal control signals. For example, you can switch inputs for 2-input muxes.

Input Signals

Internal Control Signals

These are the signals that the control unit uses for communication with the datapath.

For sel_mux[3:0], you can freely change the assigned signals if you think it would be helpful. Since they are internal control signals, it does not affect the interface of the fetch unit.

Output Signals

Test Benches

You will use provided test benches to validate your fetch unit implementation. The provided test benches are made with the following assumptions.

For Q1~Q4 below, you need to do the following things.

It is fine to include only 'interesting parts' of the simulation in your report. However, make sure that your simulation results are clearly shown and all the relevant signals are included in the capture screen. Your answers will be judged according to the degree with which they are both complete and concise.




branch.tfw simulates the execution of the following program.

addr  instruction
#0    nonbranch_op0
#1    nonbranch_op1
#2    conditional branch to #7(predicted taken)
#3    nonbranch_op3
#4    nonbranch_op4
#5    nonbranch_op5
#6    nonbranch_op6
#7    jump to #0

Write Your Own Test Bench

Now it is time to write your own test bench. Make a test bench which simulates the case when 'restart' and 'load_store_valid' signals are simultaneously asserted while the FIFO is full. Assume that the 'deque' signal is asserted 2 cycles after 'restart' and 'load_store_valid' are asserted. Make sure to set the timing configuration as the figure below. To meet the setup time requirement, you should assert inputs at negative(falling) egdes. Although your fetch unit will be graded against TA's test bench, please submit your test bench files(*.tfw, *.tbw) with other verilog files. The correctness of your fetch unit against TA's test bench will be graded. (10p)

Performance Evaluation

Now that you have tested operations of your fetch unit, it is time to evaluate its performance. As you did in lab 2, you will use the static timing report generated by Xilinx ISE. To generate a detailed report, you should change the static timing report properties as follows. First, launch 'Process Properties' window by selecting 'Properties' menu on the 'Generate Post-Place and Route Static Timing' item.

Set 'Report Type' as 'Verbose Report' and 'Perform Advanced Analysis' to on. You can see much more detailed static timing report with this setting.



  • No lab interview is required for lab 3.
  • You and your partner should submit your source files (*.v, *.tbw, *tfw zipped) via e-mail to TA before the beginning of the class. Your email title should be "[CSE141L] lab 3, SID, your_name your_partners_name".
  • Also submit your hardcopy report to TA at the beginning of the class. Please include your full source code in the report

Due: February 1