cse141L Lab 2: Fetch Unit - Datapath


January 19

Reminder: Lab 2 is to be completed in groups of two. Select your partner wisely. I'm very hesitant to allow changes to group membership once they have formed. You and your partner should submit a single write up, etc.

Due: January 25


In Lab 2, you will implement the datapath part of a decoupled fetch unit on "front end" we covered in the class. You will complete the implementation of the fetch unit in Lab 3 by adding controls, and use it as part of your future labs.

Getting Started

Starter Files

Fetch Unit Interface

module fetch#(parameter I_WIDTH = 17, A_WIDTH = 10, O_WIDTH = 5)
    input	clk,
    // inputs from the exec unit
    input	deque,
    input	restart,
    input	[A_WIDTH-1 : 0]	restart_addr,
    // memory interface
    input	load_store_valid,
    input	store_en, 
    input	[A_WIDTH-1 : 0] load_store_addr,    
    input	[I_WIDTH-1 : 0]  store_data,        
    output	[I_WIDTH-1 : 0]  load_data,
    output	load_data_valid,
    // ouputs to the exec unit    
    output	[I_WIDTH-1 : 0]	instruction_data,
    output	[A_WIDTH-1 : 0]	instruction_addr,
    output	instruction_valid

Fetch Unit Specification

Datapath Implementation

You need to thoroughly understand the specification of the fetch unit and the provided datapath schematic to answer the following questions. To do so, you think about all of the scenarios that could happen in the fetch unit datapath, and a reasonable way to handle it. Your answers will be judged according to the degree with which they are both complete and concise. In these exerices except Q5, assume the fifo never fills up.

Q1. (10p) Suppose that the address of the last fetched instruction (pc_prev_r) is 0x12. If the P bit of the last fetched instruction is 0, what is the address of the next fetched instruction? Assume that restart signal is not asserted. This functionality uses an adder, as shown in the datapath schematic. To implement it, complete the adder.v file according to the given interface using RTL verilog. Also complete mux.v file to implement connected muxes.

Q2. (10p) What is the binary encoding of an instruction which branches to the instruction located right before the current instruction? If the address of the current instruction is 0x13, it should branch to 0x12. Use 'x' for don't care bits. Explain briefly how this case would be handled in the given datapath. Complete signext.v according to the given interface to implement this part of the datapath. (Hint: You can duplicate a bit N times by {N{1'bx}} in verilog. For example, 5'b11111 can be briefly expressed by {5{1'b1}}. )

Q3. (10p) Envision the following scenario. Unfortunately, the exec unit found that the branch prediction in the fetch unit was wrong. How can it generate the 'right' address for the fetch unit? If the exec unit sent 'restart' and 'restart_addr' at cycle 10, when can the exec unit get the 'right' instruction in the best case? Explain.

Q4. (10p) Look at the datapath. You can see 'pc_prev_r' can be used for the 'pc' and can be fed to the SRAM. Considering that 'pc_prev_r' saves the "previous pc", it looks strange to use the same address for 2 cycles in a row. Why is this path needed? Explain.

Q5. (10p) Envision the following scenario.

List all the address values fed to the address port of the SRAM from cycle 0 to cycle 7 with explaination.

Q6. (50p) Complete the datapath in fetch.v using the following guidelines.

Usefule Resources


  • No lab interview is required for lab 2.
  • You and your partner should submit your source files (*.v, zipped) via e-mail to TA before the beginning of the class. Your email title should be "[CSE141L] lab 2, SID, your_name".
  • Also submit your hardcopy report to TA at the beginning of the class. Like Lab 1, your report consists of answers to the questions(Q1 ~ Q5). Please include your e-mail address in the report

Due: January 25