Homework Assignments:

• HW #1 -- Due January 19
• P&H 2.2, 2.4, 2.6, 2.8, 2.29, 2.31, 2.32, 2.37 (just rows 2,3,4,9,11)
• HW #2 -- Due January 31
• P&H 4.1, 4.2, 4.9, 4.17, 4.22, 4.40, 4.45, 4.46, P1, 3.3, 3.4, 3.10
• P1 -- Machine B runs at 2 GHz and has a CPI of 1.3 for a particular program. Machine C, which runs at 5 GHz, has a CPI of 2.4 for that program, while executing 20% more instructions. Which machine is faster? What is the speedup over the slower machine?
• HW #3 -- Due February 7
• P&H 3.11, 3.28, 3.30, 3.38, 5.2a,d,e, 5.10, 5.12, P2
• 5.12 has a typo. There is a reference to the previous problem (5.11), which mistakenly points you to 5.12.
• P2 -- Give an example of one Intel IA32 instruction that could not be implemented on a single-cycle processor, assuming reg file and memory elements similar to what we used in class.
• HW #4 -- Due February 17 (can be turned in Feb 22 - no late hws, please)
• P&H P3, P4, 5.36, 6.1 (note 1), 6.2, 6.6, 6.14, W1
• P3 -- This is the same as 5.32, except solve it for the instruction "subi". Show changes, if necessary, to the datapath and control FSM.
• P4 -- This is the same as 5.32, except solve it for the instruction "return", which jumps to the address specified by r31 (presumably stored there by a previous jal. Show changes, if necessary, to the datapath and control FSM.
• note 1 -- as in the example in the book, just assume all lw instructions, for simplicity.
• W1 -- Using the web, find the number of pipeline stages for the following processors: Intel Pentium 4, AMD Athlon 64, Intel Itanium 2.
• for a few problems, you may find this figure or this figure helpful.
• HW #5 -- Due March 2
• P&H 6.13 (note 1), 6.18, 6.21 (note 2), P5, P6
• P5 -- Circle all of the instructions in the following code that could safely be moved into the branch delay slot (replacing the nop). Assume other instructions cannot be reordered or changed. Assume you know nothing about the missing code (the ...).

  add R1, R2, R3
  sub R5, R2, R3
  and R7, R5, R2
  lw R8, 1000(R5)
  beq R7, r15, label:
  nop
  add R6, R7, R5
  sub R5, R7, R5
  lw R9, 2000(R2)
  ...
  label: add R9, R7, R5
  addi R5, R0, #0
  ...
  

• P6 -- Show forwarding and stalls for the following code, assuming the pipelined machine from figure 6.36. Show it the way we did in class, with IF ID EX M WB, and arrows and bubbles.

  lw R3, 100(R5)
  add R6, R3, R2
  sub R9, R3, R8
  lw R1, 2000(R9)
  add R5, R4, R3
  subi R7, R1, #8

• note 1 -- Please use this figure, rather than the one referenced in the problem. In this problem, you can ignore the "state why" for fields you cannot determine (just be sure you really can't).
• note 2 -- remember that "without forwarding" also implies no register file forwarding.
• HW #6 -- Due March 16
• P&H P7, 7.4, 7.9 (note 1), 7.10 (note 1), P8, 7.28, 7.32, 7.35, 7.39, W2
• P7 -- Assume the same code as P6, but running on a different pipeline. In this case, the machine has the following stages: IF ID X1 X2 M1 M2 WB. That is, ALU computation takes two cycles/stages, as does data memory access (the data needed for the alu or memory must be available at the beginning if X1 or M1, and the results are not available until the end of X2 or M2, respectively). Show forwarding and stalls for the code.
• note 1 -- To be consistent with our discussions in class, multiply all addresses in the problem by 4 to get the byte addresses. Thus, addresses are 8, 12, 44, ... (this will not change the answers).
• P8 -- Give the total size of implementation (data, tags, valid, lru, dirty) for the following cache: 128 KB cache, 4-way set associative, 64-byte block size, write-back. Assume addresses are 32 bits.
• W2 -- What are the on-chip cache configurations for the following processors: Alpha 21364, Pentium 4, AMD Athlon 64, Itanium 2?

Note, the homework may include some problems on the CD and not in the book, and even include some problems ("For More Practice" from the CD) for which they make the solutions readily available. For those ("for more practice") problems only, you may consult the answers, but please do so only after solving them (then you can go back and correct).

Very approximate Reading and Exam Schedule:
 

Date	Topic	Critical	Important	Informative
Jan 10	Introduction	1.2	-	1.1, 1.3, 1.4
Jan 12	ISA	2.1-2.6,2.9	2.13,2.15,2.16	2.7,2.8,2.10-2.12
Jan 17	ISA	-	-	-
Jan 19	Performance	4.1-4.3,4.5	4.4	-
Jan 24	Computer Arithmetic	3.1-3.4,B.5		B.6
Jan 26		3.5-3.6	3.8	3.7
Jan 31	Single-Cycle CPU	5.1,5.3,5.4	5.2
Feb 2	Single-Cycle CPU Control, Multi-cycle CPU	5.5		C.3
Feb 7	Microprogramming and Exceptions	5.6		5.7
Feb 9	Pipelining	6.1,6.2
Feb 14	Data Hazards	6.4,6.5
Feb 16	Midterm
Feb 21
Feb 23	Control Hazards	6.6		6.8
Feb 28	Advanced Pipelining	6.9, 6.10
Mar 2	Cache Basics	7.1-7.2
Mar 7	Better Caches	7.3, 7.5	7.6
Mar 9
Mar 14
Mar 16
Mar 24	Final, 11:30