Lectures in pdf format

• Lecture 1: Introduction, Chapter 1 and 2
• Lecture 2: Chapter 2 and Chapter 4
• Lecture 3: Chapter 4
• Lecture 4: Finish Chapter 4, Chapter 5
• Lecture 5: Chapter 5: single cycle CPU
• Lecture 6: Chapter 5: single cycle and multicycle CPU
• Lecture 7: Chapter 5: multicycle CPU
• Lecture 8: Chapter 5: multicycle CPU and microprogramming
• Lecture 9: Chapter 5: exceptions and review
• Lecture 10: Midterm review and Chapter 6: Pipelining
• Lecture 11: Chapter 6: Pipelining and Data Hazards
• Lecture 12: Chapter 6: Data Hazards and Control Hazards
• Lecture 13: Chapter 6: Branch Hazards (guest lecture)
• Lecture 14: Chapter 7: Cache introduction (we'll return to exceptions in pipelines next week)
• Guest lectures (now both active!) : Multicore Processors and Multithreaded Architectures
• Lecture 15: Chapter 6&7: Pipeline Exceptions and Caches
• Lecture 16: Chapter 7: Caches, Performance Issues, Stores, and More
• Lecture 17: Chapter 7:More Caches and Virtual Memory
• Lecture 18: Chapter 7: Virtual Memory, Ending things