CSE141L: Introduction to Computer Architecture Lab

When & Where

Warren Lecture Hall 2205

Lecture: MW 6:00p - 6:50p

Instructor

Hung-Wei Tseng
email: h1tseng+CSE141LSU19 @ cs.ucsd.edu
Office: 3236
Office Hours: W 6p-9p or by appointment

Teaching Assistants

Ping Yin
e-mail: piyin @ eng.ucsd.edu
Lab hours: TuTh 3p-6p

Calendar

URL http://goo.gl/VSL97g. This is just a reference for office hours. You should check Schedule and Slides for more details.

Course Discussion Board

TritonEd. Required reading. Get signed up.
Piazza:https://piazza.com/class/jxfmqa8wajk20v You should also be subscribed to the discussion forums for the course.

Course Description

This is the laboratory class associated with cse141: Introduction to Computer Architecture. Over the course of the quarter, you will design a processor that implements a large subset of the MIPS instruction set architecture. It will provide you the chance to grapple first-hand with the issues of processor design.

Text books

Required: Patterson & Hennessy, Computer Organization and Design: The Hardware/Software Interface, Patterson & Hennessy, Morgan Kaufmann, 5th Edition

Grading

There are two ways to get an "A" in this class. One is to implement a working pipelined MIPS processor by the end of the quarter that executes simple programs compiled using the GCC cross compiler. This is the grading option you should strive for. You can get an "A+" by adding some interesting and exciting feature to your processor during the final lab.

Doing well (i.e., getting an "A" or "A+") in the course will also demonstrate your ability to build a large, complex computer system.

The other way to get a good grade is to do well on the labs. If your processor doesn't turn out as well, I will consider your performance on the labs and participation (see below). Your grade will be at least the maximum of the "your processor works" grade and the lab assignment grade.

In addition to the labs, you should be an active contributer to the web board. The tools are challenging and sometimes buggy. Your classmates (in addition to the course's staff) are an excellent resource for help with the tools.

This class is about doing. You will learn almost everything you learn in this class by doing it. This means that you (or your team) must do all your own work. As long as you meet this criteria, you can consult with and discuss your project with other groups. We have structured the course (by not having a curve) so that there is no incentive to be stingy with your knowledge of the tools or in sharing your expertise with your classmates.

Late lab write ups If you cannot complete you lab on time, you can turn it in late, but your grade will be penalized. The penalty is one letter grade per 24 hours extension. Up to 2 extensions are possible. For example, if the labs are due at 5pm, you have until 5pm the next day to turn it in with one letter grade penalty, and until 5pm the day after to turn it in with a two letter grade penalty, and so on.

Keep in mind that even if your lab write up is late, you are still responsible for completing the lab, since the labs build on one another.

Labs 100% There are five labs of equal weight.

Your score will be available on TritonEd. Your final grade is the weighted average of these grades.
We do our best to record grades accurately, but you should double-check.

Errors in grading If you feel there has been an error in how an assignment or test was graded, you have one week from when the assignment is return to bring it to our attention. You must submit (via email to the instructor and the appropriate TAs) a written description of the problem. Neither I nor the TAs will discuss regrades without receiving an email from you about it first.
For arithmetic errors (adding up points etc.) you do not need to submit anything in writing, but the one week limit still applies.

If you have a problem with your final grade in the course, send me email and we can set up an appoinment to discuss it.

Schedule and Slides

DateTopicNotesSlides
2019/07/01Introduction and Lab 1 PreviewTips for using Altera tools Introduction
Verilog
2019/07/03Lab 2 Preview Lab 2
2019/07/08Lab 1 Due
2019/07/10Lab 3 Preview Lab 3
2019/07/11Lab 2 Due
2019/07/17Lab 4 Preview Lab 4
2019/07/18Lab 3 Due
2019/07/24Lab 5 Preview Lab 5
2019/07/25Lab 4 Due
2019/08/03Lab 5 Due

Integrity Policy

Labs

Lab1: Be a hardware hacker!

Lab2: Single cycle datapath!

Lab3: Single cycle control!

Lab4: Single-Cycle with Branches!

Lab5: Pipelined MIPS Processor