CSE141: Introduction to Computer Architecture

When & Where

Warren Lecture Hall 2111

Lecture: MW 2:00p - 3:20p, 3:30p-4:50p

Discussion Section:
Th 5:00p - 6:50p (WLH 2205)

Instructor

Hung-Wei Tseng
email: h1tseng+CSE141SU19 @ cs.ucsd.edu
Office: EBU3B 3236
Office Hours: MW 11a-12p or by appointment

Teaching Assistants

Yuet Fung
email: y2fung @ eng.ucsd.edu
Office:
Office Hours: TF 10a-11a @ CSE B240A or by appointment

Calendar

URL http://goo.gl/JJyrXp. This is just a reference for office hours. You should check Schedule and Slides for more details.

Course Discussion Board

TritonEd. Required reading. Get signed up.
Piazza: https://piazza.com/class/jxeaphnxi669c

Podcasting

https://podcast.ucsd.edu/watch/s119/cse141_a00

Course Description

This course will describe the basics of modern processor operation. Topics include computer system performance, instruction set architectures, pipelining, branch prediction, memory-hierarchy design, and a brief introduction to multiprocessor architecture issues.

This course is taught in tandem with CSE141L. Unless you have discussed it with you me, you should be in enrolled in both.

Text books

Required: Patterson & Hennessy, Computer Organization and Design: The Hardware/Software Interface, Patterson & Hennessy, Morgan Kaufmann, 5th Edition

Required: Other assigned readings throughout the quarter.

Optional: The History of Computing This a great set of lectures from a course taught at UCSD/UW/Berkeley three years ago. Most of them are by the folks that actually made the history (Steve Wozniak, Ray Ozzie, Gordon Bell, etc.)

Grading

Homework 15%

Homeworks will be assigned throughout the course.

Class participation 9% (Clicker-based)

We will be using clickers in the class!

Class participation 1% (Bonus)

Reading Quizzes 15%

We will have reading quizzes on TritonEd!

Midterm 25%

Final 35%

The final will be cumulative.

Additional notes about grades in this course:

  1. Your score will be available on TritonEd. Your final grade is the weighted average of these grades.
    We do our best to record grades accurately, but you should double-check.

  2. Errors in grading If you feel there has been an error in how an assignment or test was graded, you have one week from when the assignment is return to bring it to our attention. You must submit (via email to the instructor and the appropriate TAs) a written description of the problem. Neither I nor the TAs will discuss regrades without receiving an email from you about it first.
    For arithmetic errors (adding up points etc.) you do not need to submit anything in writing, but the one week limit still applies.

  3. For midterm and final, we do not regrade on a single problem. We will re-grade your whole test.

  4. Final grades If you have a problem with your final grade in the course, send me email and we can set up an appoinment to discuss it.

Schedule and Slides

DateTopicReadingsPre-release slidesSlidesDueNotes
2019/07/01 (2p) Introduction & ISA ISA (Preview) Introduction Demo
2019/07/01 (3:30p) ISA 2.1-2.7, 2.10, 2.8, 2.12, 2.13, 2.14 and 2.17   ISA Demo
2019/07/03 (2p) x86/Performance Evaluation 1.5-1.10 Performance (Preview) x86/Performance Reading quizzes for 1.5-1.10 due before class
2019/07/03 (3:30p) Performance Evaluation (II) Performance (II) Demo
2019/07/08 (2p) Performance (III) and Single-cycle Processor Design 4.1-4.4 Processor Design (Preview) Performance (III)/Power/Energy Homework 1 due before class
Reading quizzes for 4.1-4.9 due before class
Demo
2019/07/08 (3:30p) Pipeline processor 4.5-4.9   Processor Design (I)
2019/07/10 (2p) Pipeline Processor (II)     Processor Design (II)  
2019/07/10 (3:30p) Pipeline (III) Processor Design (III)   Demo
2019/07/15 (2p) Branch Prediction Processor Design (IV) Homework 2 due before class
Reading quizzes for 5.1-5.4 due before class
2019/07/15 (3:30p) Midterm Review Midterm Review
2019/07/17 (2p) Midterm  
2019/07/17 (3:30p) Memory and caching 5.1-5.4 Memory Hierarchy (Preview) Memory Hierarchy   Demo
2019/07/22 (2p) Memory and caching 5.1-5.4   Memory Hierarchy (II) Homework 3 due  
Demo
2019/07/22 (3:30p) Memory and caching 5.8 Memory Hierarchy (III)  
2019/07/24 (2p) Memory and caching Memory Hierarchy (IV) Reading quizzes for 5.7 due before class Demo
2019/07/24 (3:30p) Virtual Memory 5.7 Virtual Memory (Preview) Virtual Memory    
2019/07/29 (2p) Modern Processor Design 4.10 Advanced Pipeline (Preview) Advanced Pipeline

Homework 4 due before class
Reading quizzes for 4.10, 5.10 and 6.4-6.5 due before class

2019/07/29 (3:30p) Introduction to multithreaded processors 6.4-6.5 Multithreaded Processors (Preview) Advanced Pipeline and multithreaded processors
Virtual Memory (II)
  Demo
2019/07/31 (2p) Introduction to multithreaded processors (II) 6.4-6.5   Parallel Architectures (II) Demo
2019/07/31 (3:30p) Final Review   Final Review    
2019/08/02 Final          

Integrity Policy

Homework

Homework 1

Homework 2

Homework 3

Homework 4