CSE141L Lab 1: Be a Hardware Hacker!


Due: June 30

Lab 1 is a preparation stage for future labs, and consists of two parts - Altera Quartus and Verilog. In Lab 1, you will install the Altera tools and follow a step-by-step tutorial to learn essential concepts and working flow in hardware designs. For those who used Altera Quartus in 140L, this lab should be very easy. Otherwise, you should START NOW - there might be many unexpected problems. If you have any question regarding this lab, please post it on the discussion forum.

Please follow the course coding standards for verilog here (special Thanks to 2012 Winter CSE141L staff).

Tools:

The main verilog development tools we use in this class are Altera's Quartus II Web Edition (version 15) and ModelSim-Altera Starter. Both of these tools should already be on the lab machine. If you would like to install them for personal use (laptops, home desktops, etc.) here some instructions for downloading the tools:

Altera Quick Tutorial

Altera provides a good step-by-step tutorial. With this tutorial, you will be able to learn how to perform various activities in the hardware design process. It should take less than two hours to follow the tutorial.

A Simple 8 bit Adder

Now that you know how to use Altera Quartus II, we will examine a few aspects of hardware design.

Question 1: Draw a schematic for adder.v. In your schematic, you should clearly show the function of the design by using flip-flops, various gates, a comparator, an adder, and wires. Try to infer a schematic from the Verilog source, but it is fine to use a generated schematic from Quartus as long as it is detailed enough.
Question 2. Draw a schematic for your modified adder.
Question 3. How many flip flops (a.k.a. registers) are used for the design? How many combinational functions does the Cyclone IV E EP4CE40F29C6 have, and how many combinational functions does your design use? How many IO Pins are used?
Question 4. What is the minimum achievable cycle time and maximum frequency? What is the slack? Since we didn't specify a target clock cycle, what period and frequency did the tools use as a default target?
Question 5. Put two simulation results(behavioral and post-route) in your report. Are they the same? If not, why are they different? Modify the test bench file, and make sure post-route simulation works correctly. (Hint: Behavioral simulations do not have a sense of frequency while post-route simulations do.)

32 bit Adder

Question 6. After you reported to your boss that bigger designs tend to be slower and use more resources, he is concerned about your adder's resource usage and the maximum operational frequency. To relieve his worries, fill out the following table. To impress him even more, include 16bit and 64bit adders, too.

Width Max Freq # of used 3 input combinational functions # of used IO Pins
8 bit
16 bit
32 bit
64 bit

Useful Resources

Deliverable

  • No lab interview for lab 1. In future labs, you will have interview sessions with a TA to show your results.

  • Sent your report as a single pdf file through tritoned. The deadline for submitting your report is Thursday June 30th 11:59PM .

    • Answer all of the questions (6) found in the lab description.

    • The report should be in a single PDF file (including answers to questions, verilog source code, graphs, screen-shots, etc). There are many tools out there capable of integrating text and graphics and producing PDF files (OpenOffice does a pretty good job).

Due: June 30